Hybrid Lead Signal Integrity Engineer - High-Speed SerDes

AMD; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Hybrid work

Benefits at a glance

Job summary

AMD is seeking a Signal Integrity Engineer in the Adaptive and Embedded Computing Group. You will analyze, model and validate high-speed interconnects for SerDes channels, memory interfaces, and Ethernet links to ensure reliability and efficiency across AMD’s next-generation products.

You will collaborate with board designers, IC packaging, PCB teams, and external partners to drive accurate SI guidelines and successful first-time outcomes. This role supports hybrid work arrangements.

Qualifications

• Masters or PhD degree required in Electrical/Computer Engineering or related field.
• Proven expertise in high-speed signal integrity engineering.
• Proficiency with SI simulation tools and high-speed interfaces such as PCIe/Ethernet/DDR.

Responsibilities

• Model and simulate end-to-end high-speed channels including transceivers and PCB/package.
• Perform time/frequency domain SI analyses using industry tools.
• Identify loss, reflection, and crosstalk; implement design fixes.
• Run channel simulations to optimize Eye Diagram, BER and SNR.
• Provide board material, stack-up, and layout guidelines.
• Review PCB layout and material; propose SI/PI solutions.
• Support lab validation and correlate with simulation data.
• Collaborate with cross-functional teams to keep projects on schedule.

Skills

High-speed SI engineering

Cross-functional collaboration

MATLAB/Python data analysis

Education

Masters or PhD in Electrical Engineering

Tools

Keysight ADS

Cadence Sigrity

Ansys HFSS

Job description

AMD is seeking a Signal Integrity Engineer in the Adaptive and Embedded Computing Group. You will analyze, model and validate high-speed interconnects for SerDes channels, memory interfaces, and Ethernet links to ensure reliability and efficiency across AMD’s next-generation products.

You will collaborate with board designers, IC packaging, PCB teams, and external partners to drive accurate SI guidelines and successful first-time outcomes. This role supports hybrid work arrangements.