Hybrid IP Verification Engineer - Entry Level

Intel Corporation; Santa Clara (CA); Hybrid; USD 106,000 - 149,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Paid vacation

Job summary

Intel Corporation in Santa Clara, California is hiring an IP Design Verification Engineer at the college graduate level to verify complex IP designs using SystemVerilog, UVM, and other industry-standard tools.

The role emphasizes hands-on test plan development, debugging, and documentation, with a hybrid on-site/off-site work model and a compensation package including stock bonuses, health benefits, and retirement options.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 0+ year of hands-on experience, entry level.
• Experience with Verilog/VHDL, SystemVerilog and UVM is preferred.

Responsibilities

• Develop and implement test plans and verification strategies for IP designs.
• Identify, debug, and resolve design and verification issues to ensure quality.
• Collaborate with cross-functional teams to address challenges.
• Generate comprehensive documentation for verification processes and test results.
• Improve verification efficiency through automation and innovative practices.

Skills

Verilog

VHDL

SystemVerilog

UVM

Python scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Job description

Intel Corporation in Santa Clara, California is hiring an IP Design Verification Engineer at the college graduate level to verify complex IP designs using SystemVerilog, UVM, and other industry-standard tools.

The role emphasizes hands-on test plan development, debugging, and documentation, with a hybrid on-site/off-site work model and a compensation package including stock bonuses, health benefits, and retirement options.