Hybrid Pre-Silicon Clock IP Verification Engineer

Intel Corporation; Phoenix (AZ); Hybrid; USD 122,000 - 173,000; Full time

Job summary

Intel Corporation seeks an IP Design Verification Engineer to verify clock generator IPs (PLL/FLL) across Intel's product development cycle. You will build verification environments, run tests in SystemVerilog/UVM, and debug pre-silicon issues to meet strict specifications.

You will collaborate with architects, RTL and analog teams, lead AMS validation activities, and help evolve IP verification methodologies across multiple generations.

Qualifications

• Design verification methodologies (UVM, SystemVerilog, EDA).
• Scripting languages such as Python and Perl.
• Expertise in SystemVerilog UVM coding and debugging.
• Familiarity with PLL/FLL or SOC clocking and RTL development.

Responsibilities

• Develop test benches, verification environments, and tests using System Verilog and UVM.
• Perform functional verification for clock generator IPs like PLL and FLL.
• Maintain and refine verification infrastructure for multiple IP generations.
• Debug and root-cause pre-silicon issues in the verification environment.
• Document test plans and participate in technical reviews with design teams.
• Collaborate with architects, RTL developers, and analog design teams.
• Lead Mixed Signal Validation activities, including AMS simulations and schematic debugging.
• Contribute to architectural and microarchitectural feature definitions for IP design.

Skills

SystemVerilog

UVM

Python

Perl

Test benches

Debugging

Education

Bachelors in Electrical or Computer Engineering

Masters in Electrical or Computer Engineering

PhD in Electrical or Computer Engineering

Tools

EDA tools

Job description

Intel Corporation seeks an IP Design Verification Engineer to verify clock generator IPs (PLL/FLL) across Intel's product development cycle. You will build verification environments, run tests in SystemVerilog/UVM, and debug pre-silicon issues to meet strict specifications.

You will collaborate with architects, RTL and analog teams, lead AMS validation activities, and help evolve IP verification methodologies across multiple generations.