AI-Driven Design Verification Engineer - Entry Level

Intel Corporation; Santa Clara (CA); On-site; USD 106,000 - 149,000; Full time

Job summary

Intel Corporation in Santa Clara, CA, is seeking an Entry Level Design Verification Engineer to help verify interconnect and chassis IPs for next-generation SoC platforms. You will work with senior engineers, build testbenches, and develop constrained-random tests while ramping quickly.

You'll learn verification flows, write and debug tests, analyze failures, and contribute to coverage plans, with opportunities to apply AI-assisted development tools in daily tasks. On-site role.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science and 3+ months of internship experience in a hardware design or verification environment.
• Foundation in logic design and digital circuits – required; ability to read and reason about RTL is essential.
• Demonstrated proficiency in at least one of C/C++, Python, or SystemVerilog through coursework, projects, or internships.
• Demonstrated use of AI coding assistants as a regular part of coursework or project work - not occasional use, but as a genuine productivity tool.

Responsibilities

• Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers.
• Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups.
• Contribute to functional coverage plans, coverage closure analysis, and regression triage.
• Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries.
• Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting.
• Continuously build depth in hardware design, verification methodology, and the chip development flow.

Skills

C/C++

Python

SystemVerilog

RTL reading

Algorithmic thinking

Education

BS or MS in Electrical Engineering/Computer Engineering/CS

Tools

ModelSim

VCS

Questa

Linux

Git

Build/Automation scripts

Job description

Intel Corporation in Santa Clara, CA, is seeking an Entry Level Design Verification Engineer to help verify interconnect and chassis IPs for next-generation SoC platforms. You will work with senior engineers, build testbenches, and develop constrained-random tests while ramping quickly.

You'll learn verification flows, write and debug tests, analyze failures, and contribute to coverage plans, with opportunities to apply AI-assisted development tools in daily tasks. On-site role.