Entry-Level Design Verification Engineer - AI-Driven HW Testing

Intel; Santa Clara (CA); On-site; USD 106,000 - 149,000; Full time

Job summary

Intel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team to contribute to the verification of interconnect and chassis IPs underpinning Intel's SoC and platform products.

You will work with senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures — developing end-to-end verification skills from day one. This college-grad role is on-site in Santa Clara, CA.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science with 3+ months of internship in hardware design or verification.
• Foundational knowledge of logic design and digital circuits - reading RTL is essential.
• Demonstrated algorithmic thinking and software fundamentals.
• Proficiency in at least one of C/C++, Python, or SystemVerilog through coursework or internships.
• Exposure to AI coding assistants as part of coursework or projects.

Responsibilities

• Develop testbench components, constrained-random stimulus, and functional checkers for interconnect and chassis IP under guidance of senior engineers.
• Write, run, and debug simulation tests; analyze failures and root-cause issues to closure with clear technical write-ups.
• Contribute to functional coverage plans, coverage closure analysis, and regression triage.
• Participate in spec reviews, design discussions, and bug triage; learn to contribute across architecture, design, and software boundaries.
• Use AI-assisted coding and debugging tools as an everyday part of development workflow; actively contribute to the team's productivity through automation and scripting.
• Continuously build depth in hardware design, verification methodology, and the chip development flow.

Skills

C/C++

Python

SystemVerilog

Education

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science

Tools

ModelSim

VCS

Questa

Git

Linux

Job description

Intel is seeking an Entry Level Design Verification Engineer for the Silicon Chassis team to contribute to the verification of interconnect and chassis IPs underpinning Intel's SoC and platform products.

You will work with senior engineers to build testbenches, write constrained-random tests, close functional coverage, and root-cause simulation failures — developing end-to-end verification skills from day one. This college-grad role is on-site in Santa Clara, CA.