Hybrid Field Application Engineer: Verif & SoC Solutions

Siemens Mobility

Santa Clara (CA)

On-site

USD 150,000 - 193,000

Full time

5 days ago
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Benefits offered by this job

Health benefits
Paid time off
Parental leave

Job summary

Siemens Industry Software Inc. in Santa Clara, CA is seeking a Field Application Engineer to provide technical leadership in verification technologies for leading customers. You will integrate DVT products, assess customer environments, and ensure the solutions meet design and verification objectives.

The role requires experience with HDL, SystemVerilog/UVM, testbenches, and automation in Python/Perl/C++. Up to 25% travel is expected; a hybrid work model is available.

Qualifications

  • Design and implement digital logic using HDLs (Verilog, VHDL) and verification methods.
  • Develop advanced test benches and simulate complex SoC environments with automation scripts.
  • Troubleshoot RTL/verification environments and optimize regression performance.
  • Analyze semiconductor IC tech, including ASIC/SoC architectures and memory subsystems.

Responsibilities

  • Provide technical leadership in sales and support of verification technologies for EDA customers.
  • Integrate DVT products and services and ensure expected behavior in customer environments.
  • Assess customer environments and requirements; articulate needs to product engineering.
  • Deliver training and consulting on advanced verification topics and promote adoption.
  • Travel up to 25% domestically; may telecommute from a commutable distance.

Skills

HDL design
SystemVerilog/UVM
Testbench development
Python automation

Tools

Python
Perl
C/C++

Job description

Siemens Industry Software Inc. in Santa Clara, CA is seeking a Field Application Engineer to provide technical leadership in verification technologies for leading customers. You will integrate DVT products, assess customer environments, and ensure the solutions meet design and verification objectives.

The role requires experience with HDL, SystemVerilog/UVM, testbenches, and automation in Python/Perl/C++. Up to 25% travel is expected; a hybrid work model is available.

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