High-Speed SERDES PHY Firmware Engineer

Cadence; San Jose (CA); On-site; USD 101,500 - 188,500; Full time

Job summary

Cadence in California is seeking a High Speed SERDES PHY Firmware Design Engineer (T1/T2) to join a dynamic, growing team of engineers developing physical IP for industry‑standard high‑speed serial‑link protocols.

The role covers firmware architecture development, implementation, verification, testing and customer deployment, with opportunities to lead project effort and collaborate across product engineering, validation and design teams.

Qualifications

• Solid programming knowledge in C/C++ and Python.
• Understanding of wireline communication principles.
• Knowledge in mixed signal circuit design and digital signal processing techniques.
• Strong problem solving and communication skills.
• BSc or MSc in Electrical Engineering.

Responsibilities

• Contribute to firmware architecture development and implementation of firmware features.
• Work with verification to debug and fix FW issues.
• Involvement during post-silicon testing and validation to identify FW/HW issues and implement FW improvements.
• Interaction with Product Engineering, System Validation and Design teams to debug IP issues in the field and provide hot fixes.

Skills

C/C++

Python

Wireline comms

Mixed-signal DSP

Problem solving

Education

BSc or MSc in Electrical Engineering

Job description

Cadence in California is seeking a High Speed SERDES PHY Firmware Design Engineer (T1/T2) to join a dynamic, growing team of engineers developing physical IP for industry‑standard high‑speed serial‑link protocols.

The role covers firmware architecture development, implementation, verification, testing and customer deployment, with opportunities to lead project effort and collaborate across product engineering, validation and design teams.