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Cadence is seeking a High Speed SERDES PHY Firmware Design Engineer to lead firmware development for industry-standard high-speed SERDES IP. You will architect, implement, verify, test, and deploy firmware, working with cross-functional teams to ensure robust IP delivery.
The role encompasses architecture development, field debugging, and collaboration with Product Engineering and System Validation to support customer deployment and ongoing improvements.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a world leader in electronic design automation and a driving force in the advancement of intellectual property. Our silicon IP portfolio exceeds 25 years of experience and is used by many of the world’s leading semiconductor and system companies. We provide an open IP platform and IP factory approach, allowing customers to design, customize, and verify IP and subsystems that fit seamlessly into their SoCs.
This role is for a team of experienced engineers developing physical IP for industry‑standard high‑speed serial‑link protocols. The successful candidate will work independently and contribute to project leadership. Responsibilities span firmware development for high‑speed SERDES from architecture creation to implementation, verification, testing, and customer deployment.
Annual salary range for Canada (CAD): $73,500 – $136,500. Eligible for incentive compensation such as bonus, equity, and benefits. Benefits include paid vacation and holidays, leave of absence programs, RRSP, TFSA, Employee Stock Purchase Plan, group health coverage (including dental, vision, and EAP), life insurance, short‑term and long‑term disability, Global Travel Medical coverage, Business Travel Accident Insurance, and Lifestyle Spending Account.