High-Speed SerDes PHY Design Engineer (Analog/Mixed-Signal)

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an analog/mixed-signal circuit designer to join the SerDes PHY team. You will work on transistor-level designs and supervise layouts for high-speed PHY blocks, with emphasis on 7nm CMOS processes and low-power techniques.

Responsibilities include simulations, design reviews, collaboration with layout teams, and documentation. A background in >32Gbps transceiver or clocking design is highly valued; strong CAD/verification experience is required.

Qualifications

• Bachelor's degree in Electrical Engineering with 2+ years of analog/mixed-signal IC design and 2+ years of ASIC design/verification.
• Master's degree in Electrical Engineering with 2+ years of ASIC design/verification.
• PhD in Electrical Engineering or related field is encouraged.
• 2+ years of experience using design tools (CADENCE, SPICE, MATLAB, Verilog/VHDL).

Responsibilities

• Contribute to architecture and circuit designs for blocks; participate in design reviews.
• Oversee block-level layout coordination with layout teams.
• Define and run simulations (power, performance); document results.
• Test designs, debug issues, and assist junior colleagues.
• Prepare detailed design documentation and collaborate across teams.

Skills

Analog design

Mixed-signal design

Transistor-level design

ASIC design/verification

Circuit simulation

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

SPICE

MATLAB

Verilog/VHDL

Job description

Qualcomm Technologies, Inc. seeks an analog/mixed-signal circuit designer to join the SerDes PHY team. You will work on transistor-level designs and supervise layouts for high-speed PHY blocks, with emphasis on 7nm CMOS processes and low-power techniques.

Responsibilities include simulations, design reviews, collaboration with layout teams, and documentation. A background in >32Gbps transceiver or clocking design is highly valued; strong CAD/verification experience is required.