High-Speed SerDes Architect & Silicon Engineer

Hardware FYI; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

AMD's Serdes Technology Group seeks an expert in analog/mixed-signal transceiver design to drive high-speed PHY development in San Jose, CA. The role focuses on transceiver micro-architecture definition, modeling, simulation, and verification, with collaboration across engineering, verification, and silicon teams.

The ideal candidate has a Ph.D. or MS with industrial experience in optical or electrical transceiver design, excellent communication, and a track record of delivering complex projects

Qualifications

• Ph.D in electrical engineering or related fields with industrial experience in optical and/or electrical transceiver design and architecture.
• Excellent communication and documentation skills are required.

Responsibilities

• Lead transceiver micro-architecture definition, modeling, simulation, implementation, and verification: Tx and Rx analog front-end blocks, clocking circuits, DSPs, CDR, adaptation and calibration loops, firmware loops, system level interface
• To work with pre-tapeout verification for silicon design sign-off and post-silicon validation teams to bring up silicon and analyze volume productization data

Skills

Link budgeting

Transceiver design

Analog design

Mixed-signal design

Micro-architecture

Modeling

Simulation

Education

Ph.D in EE or related

M.S. with relevant experience

Job description

AMD's Serdes Technology Group seeks an expert in analog/mixed-signal transceiver design to drive high-speed PHY development in San Jose, CA. The role focuses on transceiver micro-architecture definition, modeling, simulation, and verification, with collaboration across engineering, verification, and silicon teams.

The ideal candidate has a Ph.D. or MS with industrial experience in optical or electrical transceiver design, excellent communication, and a track record of delivering complex projects