High-Impact ASIC Verification Engineer

Meta; Austin (TX); On-site; USD 114,000 - 172,000; Full time

Job summary

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure Silicon organization in Austin, TX. You will own verification closure for modules and subsystems, building IP/SoC verification plans and UVM-based testbenches.

Responsibilities include debugging RTL, applying formal verification and emulation to complement simulations, and collaborating with cross-functional teams to ensure first-pass silicon success for data center applications.

Qualifications

• Bachelor's degree in CS/CE or related field, completed before joining Meta.
• 2+ years hands-on SystemVerilog and UVM or C/C++ hardware verification.
• 2+ years verification at block/IP/sub-system/SoC level using SV UVM/OVM.
• Experience with EDA simulators and scripting languages for verification environments.
• Experience debugging RTL failures in simulation or emulation environments.

Responsibilities

• Define and implement verification plans for blocks, IPs, and SoCs to achieve functional coverage.
• Develop and maintain UVM-based testbenches and sequences aligned to test plans.
• Drive verification closure using functional, code, and assertion coverage metrics.
• Debug RTL functional failures and work with ASIC design teams to resolve issues.
• Apply formal verification and emulation to augment simulations and improve efficiency.
• Collaborate with design, architecture, and post-silicon teams to align verification goals.
• Develop reusable verification components like scoreboards, monitors, and coverage models.
• Create automation scripts to improve regression productivity and flows.
• Participate in design reviews and verification planning to identify risks.

Skills

SystemVerilog

UVM

C/C++

Python scripting

RTL debugging

Emulation

Formal verification

Testbench development

Education

Bachelor's degree in Computer Science/Computer Engineering

Tools

EDA simulators

Scripting tools (Python, TCL, Perl, Shell)

Job description

Meta is seeking an ASIC Design Verification Engineer to join the Infrastructure Silicon organization in Austin, TX. You will own verification closure for modules and subsystems, building IP/SoC verification plans and UVM-based testbenches.

Responsibilities include debugging RTL, applying formal verification and emulation to complement simulations, and collaborating with cross-functional teams to ensure first-pass silicon success for data center applications.