HBM PHY Design Intern: AI-Driven Automation & Verification

Micron Technology, Inc; Richardson (TX); On-site; USD 34,000 - 48,000; Full time

Job summary

Micron Technology, Inc. in Richardson, TX, seeks a Senior or Graduate Engineering Intern to join the Heterogeneous Integration Group (HIG) HBM Architecture team.

You will support digital design methodologies, timing analysis flows, and architecture validation for next‑generation HBM PHY/IO subsystems. The role provides hands‑on experience in digital design, verification, automation, and timing analysis, with exposure to AI-assisted engineering and Generative AI tools to boost productivity and

Qualifications

• Currently pursuing a Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong understanding of digital design concepts including FSMs, pipelining, clock-domain crossing, timing analysis, and computer architecture.
• Experience with RTL design and verification concepts using Verilog or SystemVerilog.
• Proficiency in Python, C++, or a comparable language; Linux-based development.

Responsibilities

• Support digital design, integration, and timing analysis for HBM PHY/IO subsystems, including timing constraint development and closure.
• Develop and verify using Verilog/SystemVerilog and UVM-based environments; analyze simulations and debug timing issues.
• Create Python-based automation tools and AI-assisted workflows to improve engineering efficiency.
• Collaborate with architecture, design, verification, and product teams to validate architectures and improve design quality.

Skills

RTL design

Verilog/SystemVerilog

Python

C++

Linux

FSMs

Pipelining

CDC

Debugging

Education

Master's or Ph.D. in Electrical Engineering / Computer Engineering / Computer Science

Tools

UVM-based verification environments

Cadence

Synopsys

Siemens

Job description

Micron Technology, Inc. in Richardson, TX, seeks a Senior or Graduate Engineering Intern to join the Heterogeneous Integration Group (HIG) HBM Architecture team.

You will support digital design methodologies, timing analysis flows, and architecture validation for next‑generation HBM PHY/IO subsystems. The role provides hands‑on experience in digital design, verification, automation, and timing analysis, with exposure to AI-assisted engineering and Generative AI tools to boost productivity and