HBM Clock Design Intern — AI‑Driven Architecture

Micron Technology, Inc

Richardson (TX)

On-site

USD 34,000 - 48,000

Full time

5 days ago
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Job summary

Micron Technology, Inc. is seeking an Intern to work with Heterogeneous Integration Group engineers on evaluating HBM clocking architectures, PLL performance, timing behavior, and clock distribution strategies.

You will apply analytical modeling and AI-assisted workflows to improve design exploration and productivity. The role targets graduate students in Electrical Engineering, with knowledge of analog/mixed-signal fundamentals and clocking concepts.

Qualifications

  • Pursuing a Master's or Ph.D. degree in Electrical Engineering or related field.
  • Solid understanding of analog and mixed-signal circuit fundamentals.
  • Familiarity with clock generation and distribution concepts, including PLLs, DLLs, jitter, and timing analysis.
  • Experience with circuit simulation tools such as SPICE, Spectre, HSPICE, MATLAB, or equivalents.
  • Strong analytical, debugging, and communication skills.

Responsibilities

  • Analyze and document HBM clocking architectures, including clock distribution networks, WDQS timing architecture, and PLL design concepts.
  • Evaluate clock noise sensitivity, timing margins, jitter performance, and PLL impacts on high-speed IO signal quality.
  • Benchmark and compare alternative clock architecture solutions and provide data-driven recommendations.
  • Find opportunities for performance optimization and support architecture-level design decisions.
  • Apply LLMs, Generative AI, and AI-assisted workflows to enhance engineering analysis and productivity.

Skills

Analog/mixed-signal fundamentals
Clock generation & distribution
Analytical problem solving
Communication skills
Python programming

Education

Master's or Ph.D. in Electrical Engineering

Tools

SPICE
Spectre
HSPICE
MATLAB

Job description

Micron Technology, Inc. is seeking an Intern to work with Heterogeneous Integration Group engineers on evaluating HBM clocking architectures, PLL performance, timing behavior, and clock distribution strategies.

You will apply analytical modeling and AI-assisted workflows to improve design exploration and productivity. The role targets graduate students in Electrical Engineering, with knowledge of analog/mixed-signal fundamentals and clocking concepts.

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