HBM Clocking Architect Intern — AI-Driven Design

Micron; Richardson (TX); On-site; USD 28,000 - 41,000; Full time

Benefits offered by this job

Medical coverage

PTO

Paid holidays

Job summary

Micron Technology is seeking a motivated Intern to join the Heterogeneous Integration Group (HIG) HBM Architecture team in Richardson, TX. You will evaluate HBM clocking architectures, PLL performance, and timing behavior while applying AI-assisted engineering workflows to improve design exploration and productivity.

You will work with experienced architects to analyze clock distribution networks, assess jitter performance, and benchmark alternative solutions for data-center and AI/HPC

Qualifications

• Currently pursuing a Master’s or Ph.D. in Electrical Engineering or related field.
• Strong understanding of analog and mixed-signal circuits fundamentals.
• Familiarity with clock generation and distribution concepts (PLLs, DLLs, jitter, timing analysis).
• Experience with circuit simulation tools such as SPICE, Spectre, and HSPICE, MATLAB, or equivalent.

Responsibilities

• Analyze and document HBM clocking architectures and PLL concepts.
• Evaluate clock noise sensitivity, timing margins, jitter, and IO signal quality.
• Benchmark and compare alternative clock architectures and provide data-driven recommendations.
• Identify opportunities for performance optimization and support architecture-level design decisions.
• Apply AI-assisted workflows to enhance engineering analysis and productivity.

Skills

Analog fundamentals

Clock generation

Circuit analysis

Education

Master's/PhD EE

Tools

SPICE

Spectre

HSPICE

Job description

Micron Technology is seeking a motivated Intern to join the Heterogeneous Integration Group (HIG) HBM Architecture team in Richardson, TX. You will evaluate HBM clocking architectures, PLL performance, and timing behavior while applying AI-assisted engineering workflows to improve design exploration and productivity.

You will work with experienced architects to analyze clock distribution networks, assess jitter performance, and benchmark alternative solutions for data-center and AI/HPC