HBM 3D Power Delivery Network (PDN) Engineer

Micron Technology; Folsom (CA); On-site; USD 146,000 - 297,000; Full time

Benefits offered by this job

Comprehensive medical, dental, and vision plans

Paid family leave

Robust paid time‑off program

Paid holidays

Job summary

Micron Technology is seeking an HBM Power Delivery Network Engineer in Folsom, California, to design, analyze, and optimize power delivery networks for next-generation HBM products. This role focuses on ensuring efficiency and manufacturability while achieving aggressive performance targets.

The ideal candidate will have substantial experience in power delivery network design, a solid understanding of EM/IR analysis tools, and a background in mentoring junior engineers. Excellent analytical skills and a degree in Electrical Engineering are required.

Qualifications

• Strong experience in power delivery network design and analysis for complex SoCs or high‑performance ASICs.
• Solid understanding of IR drop, electromigration, dynamic voltage droop, and power‑noise mechanisms.
• Proven ability to mentor and develop junior engineers.

Responsibilities

• Design and develop SoC‑level and HBM‑cube‑level power delivery networks.
• Perform EM/IR analysis and optimization using industry‑standard tools.
• Collaborate with physical design teams on floorplanning and routing strategies.

Skills

Power delivery network design

EM/IR analysis tools

Debugging skills

3D modeling of PDN networks

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Cadence RedHawk

Ansys Totem

Job description

Job Summary

As an HBM Power Delivery Network (PDN) Engineer, you will be part of the Heterogeneous Integration Group (HIG). Your core responsibilities will include designing, analyzing, and optimizing power delivery networks for next‑generation HBM products, ensuring robust, efficient, and manufacturable solutions that meet aggressive performance, power‑integrity, and reliability targets.

Key Responsibilities

• Design and develop SoC‑level and HBM‑cube‑level power delivery networks, including power‑grid architecture, routing strategies, and decoupling schemes.
• Perform EM/IR analysis and optimization using industry‑standard tools such as Cadence RedHawk or Ansys Totem to ensure power integrity across dynamic workloads.
• Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation.
• Drive power‑integrity closure across multi‑mode/multi‑corner scenarios, identifying and mitigating droop, noise, and electromigration risks.
• Work with package and system teams to co‑optimize die‑package‑system PDN interactions, including bump/pad assignment and current distribution.
• Develop and validate power models, including activity‑based current profiles and transient analysis for realistic workload scenarios.
• Partner with architecture and design teams to influence power‑aware design decisions, including power domains, gating strategies, and current‑demand shaping.
• Support signoff activities, including EM, IR, and reliability verification, ensuring the design meets long‑term reliability and manufacturability goals.
• Debug and root‑cause PDN‑related issues during pre‑silicon and post‑silicon phases, including silicon correlation and model refinement.
• Improve PDN methodologies through automation, scripting, and best‑practice development across HBM programs.

Qualifications

• Strong experience in power delivery network design and analysis for complex SoCs or high‑performance ASICs.
• Proficiency with EM/IR analysis tools such as RedHawk, Totem, or equivalent.
• Proficiency with Spice‑based simulation tools and 3D modeling of PDN networks.
• Solid understanding of IR drop, electromigration, dynamic voltage droop, and power‑noise mechanisms.
• Experience with physical design flows and close interaction with floorplanning, routing, and implementation teams.
• Familiarity with full RTL‑to‑GDSII design flow and signoff methodologies.
• Strong analytical and debugging skills with the ability to drive complex issues to closure.

Preferred Qualifications

• Experience with HBM, DRAM, or memory‑centric SoC designs, including understanding of 3DIC power delivery challenges.
• Familiarity with die‑package‑system co‑design and advanced packaging technologies (e.g., 2.5D/3D integration).
• Experience with transient and vector‑based power analysis methodologies.
• Knowledge of JEDEC standards and memory subsystem behavior.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

Compensation

US base salary range: $146,000.00 – $297,000.00 a year. Additional compensation may include benefits, bonuses, and equity.

Benefits

Micron offers a comprehensive benefit program that includes medical, dental, and vision plans, income protection, paid family leave, a robust paid time‑off program, and paid holidays. For detailed information, please refer to the Micron Benefits Guide.

Equal Opportunity

Micron is proud to be an equal‑opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.