HBM 3D Power Delivery Network (PDN) Engineer

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 146,000 - 297,000; Full time

Benefits offered by this job

Comprehensive benefits package

Paid family leave

Paid time off

Job summary

1000 Micron Technology, Inc. is seeking an HBM Power Delivery Network (PDN) Engineer based in Richardson, Texas. This role involves designing and optimizing power delivery networks for next-generation HBM products, requiring a strong background in power delivery network design and analysis for high-performance ASICs.

The ideal candidate will have a minimum of 10 years of experience, a relevant degree, and familiarity with industry-standard analysis tools. Micron offers a competitive salary and a comprehensive benefits package aimed at supporting employee wellbeing.

Qualifications

• Minimum 10 years of experience in power delivery network design.
• Experience with high-performance ASICs or complex SoCs.
• Understanding of power integrity issues like IR drop and noise.

Responsibilities

• Design power delivery networks for next-gen HBM products.
• Perform EM/IR analysis to ensure power integrity.
• Collaborate with design teams on PDN implementation.

Skills

Power delivery network design

EM/IR analysis tools

Debugging skills

SPICE-based simulation

3-D modeling of PDN networks

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Cadence RedHawk

Ansys Totem

Job description

Overview

Micron Technology is a world leader in innovating memory and storage solutions. As an HBM Power Delivery Network (PDN) Engineer, you will be part of the Heterogeneous Integration Group (HIG), responsible for the design, analysis, and optimization of power delivery networks for next‑generation HBM products.

Responsibilities

• Design and develop SoC‑level and HBM‑cube‑level power delivery networks, including power grid architecture, routing strategies, and decoupling schemes.
• Perform EM/IR analysis and optimization using industry‑standard tools such as Cadence RedHawk and Ansys Totem to ensure power integrity across dynamic workloads.
• Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation.
• Drive power integrity closure across multi‑mode/multi‑corner scenarios, identifying and mitigating droop, noise, and electromigration risks.
• Work with package and system teams to co‑optimize die‑package‑system PDN interactions, including bump/pad assignment and current distribution.
• Develop and validate power models, including activity‑based current profiles and transient analysis for realistic workload scenarios.
• Partner with architecture and design teams to influence power‑aware design decisions, including power domains, gating strategies, and current demand shaping.
• Support signoff activities, including EM, IR, and reliability verification, ensuring the design meets long‑term reliability and manufacturability goals.
• Debug and root‑cause PDN‑related issues during pre‑silicon and post‑silicon phases, including silicon correlation and model refinement.
• Improve PDN methodologies through automation, scripting, and best‑practice development across HBM programs.

Qualifications

• Strong experience in power delivery network design and analysis for complex SoCs or high‑performance ASICs.
• Proficiency with EM/IR analysis tools such as RedHawk, Totem, or equivalent.
• Proficiency with SPICE‑based simulation tools and 3‑D modeling of PDN networks.
• Solid understanding of IR drop, electromigration, dynamic voltage droop, and power noise mechanisms.
• Experience with physical design flows and close interaction with floorplanning, routing, and implementation teams.
• Familiarity with full RTL‑to‑GDSII design flow and signoff methodologies.
• Strong analytical and debugging skills with the ability to drive complex issues to closure.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

Preferred Qualifications

• Experience with HBM, DRAM, or memory‑centric SoC designs, including understanding of 3DIC power delivery challenges.
• Familiarity with die‑package‑system co‑design and advanced packaging technologies (e.g., 2.5D/3D integration).
• Experience with transient and vector‑based power analysis methodologies.
• Knowledge of JEDEC standards and memory subsystem behavior.

Salary

The US base salary range for this full‑time position is: $146,000.00 – $297,000.00 a year. Additional compensation may include benefits, bonuses, and equity.

Benefits

Micron offers a comprehensive benefits package that includes medical, dental, and vision plans, income protection programs, paid family leave, paid time off, paid holidays, and other programs to support employees’ wellbeing.

Equal Employment Opportunity

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws. Micron prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.