HBM SoC Physical Design Engineer

Micron Technology, Inc; Folsom (CA); On-site; USD 121,000 - 205,000; Full time

Job summary

Micron Technology, Inc. is seeking a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG) to drive implementation from netlist to GDSII for advanced HBM-based designs.

You will own blocks or top-level integration and collaborate across RTL, verification, IP, packaging and manufacturing to meet PPA targets. The role emphasizes hands-on execution, signoff readiness, and contributing to AI-driven tooling and workflows to improve design productivity across multiple product

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Calibre).
• Solid understanding of STA fundamentals, clocking, SDC constraints, and closure techniques.

Responsibilities

• Own physical implementation for SoC blocks/top-levels, including floor-planning, placement, CTS, routing, and optimization for PPA targets.
• Drive timing closure across MMMC scenarios with RTL, architecture, and signoff teams.
• Coordinate integration of complex IP with robust physical integration and timing/power integrity.
• Perform and coordinate physical signoff (DRC/LVS/IR drop) and collaborate with DFT teams for scan/MBIST feasibility.
• Work with packaging and manufacturing to ensure manufacturability and quality; support tape-out and post-silicon debugging.

Skills

SoC physical design

EDA tools

STA fundamentals

Power integrity concepts

HBM/DRAM awareness

Education

Bachelor's or master's degree in Electrical/Computer Engineering or related field

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Calibre

Job description

Req ID: JR107315 HBM SoC Physical Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a SoC Physical Design Engineer in the Heterogenous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best-in-class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.

Key Responsibilities

• Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
• Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
• Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
• Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.

Required Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
• Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.

Preferred Qualifications

• Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
• Minimum 3 years of experience in a related field.
• Proven ability to mentor and develop engineers early in their careers.
• Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

Job Profile(s):

Systems Design Engineer 3

Relocation Level: TBD

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$121,000.00 - $205,000.00 a year

Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.