HBM 3D Power Delivery Network (PDN) Engineer

Micron Technology, Inc; Richardson (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Micron Technology, Inc is seeking an HBM Power Delivery Network Engineer to join their Heterogeneous Integration Group in Richardson, Texas. This role involves designing and optimizing power delivery networks for next-gen HBM products, working closely with various teams to ensure robust power solutions.

The ideal candidate will have strong experience in power delivery network design and proficiency with industry-standard analysis tools. A Bachelor's or Master's degree in Electrical Engineering and at least 10 years of relevant experience is required. The position promises an engaging and inclusive workplace.

Qualifications

• Strong experience in power delivery network design for complex SoCs.
• Proficiency with EM/IR analysis tools like RedHawk or Totem.
• Solid understanding of IR drop, electromigration, and power noise mechanisms.

Responsibilities

• Design and develop SoC-level power delivery networks.
• Perform EM/IR analysis to ensure power integrity.
• Collaborate with physical design teams on floorplanning and placement.

Skills

Power delivery network design

EM/IR analysis tools (e.g., RedHawk, Totem)

Spice-based simulation tools

Analytical and debugging skills

3D modeling of PDN networks

Education

Bachelor's or Master’s degree in Electrical Engineering

Tools

Cadence RedHawk

Ansys Totem

Job description

Job Overview

As an HBM Power Delivery Network (PDN) Engineer, you will be part of the Heterogeneous Integration Group (HIG), responsible for the design, analysis, and optimization of power delivery networks for next‑generation HBM products. You will work closely with architecture, design, physical design, packaging, and product engineering teams to ensure robust, efficient, and manufacturable power delivery solutions that meet aggressive performance, power‑integrity, and reliability targets.

Key Responsibilities

• Design and develop SoC‑level and HBM‑cube‑level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes.
• Perform EM/IR analysis and optimization using industry‑standard tools (e.g., Cadence RedHawk, Ansys Totem) to ensure power integrity across dynamic workloads.
• Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation.
• Drive power‑integrity closure across multi‑mode/multi‑corner scenarios, identifying and mitigating droop, noise, and electromigration risks.
• Work with package and system teams to co‑optimize die‑package‑system PDN interactions, including bump/pad assignment and current distribution.
• Develop and validate power models, including activity‑based current profiles and transient analysis for realistic workload scenarios.
• Partner with architecture and design teams to influence power‑aware design decisions, including power domains, gating strategies, and current demand shaping.
• Support signoff activities, including EM, IR, and reliability verification, ensuring design meets long‑term reliability and manufacturability goals.
• Debug and root‑cause PDN‑related issues during pre‑silicon and post‑silicon phases, including silicon correlation and model refinement.
• Improve PDN methodologies through automation, scripting, and best‑practice development across HBM programs.

Qualifications

• Strong experience in power delivery network design and analysis for complex SoCs or high‑performance ASICs.
• Proficiency with EM/IR analysis tools such as RedHawk, Totem, or equivalent.
• Proficiency with Spice‑based simulation tools and 3D modeling of PDN networks.
• Solid understanding of IR drop, electromigration, dynamic voltage droop, and power noise mechanisms.
• Experience with physical design flows and close interaction with floorplanning, routing, and implementation teams.
• Familiarity with full RTL‑to‑GDSII design flow and signoff methodologies.
• Strong analytical and debugging skills with the ability to drive complex issues to closure.

Preferred Qualifications

• Experience with HBM, DRAM, or memory‑centric SoC designs, including understanding of 3DIC power delivery challenges.
• Familiarity with die‑package‑system co‑design and advanced packaging technologies (e.g., 2.5D/3D integration).
• Experience with transient and vector‑based power analysis methodologies.
• Knowledge of JEDEC standards and memory subsystem behavior.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

Job Profile

Systems Design Engineer4 - Systems Design Engineer5

Relocation Level: TBD

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.