Senior SOC Physical Design Engineer, HBM

Micron Technology; Richardson (TX); On-site; USD 90,000 - 120,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time-off program

Paid family leave

Job summary

Micron Technology in Richardson, Texas is seeking an experienced SoC Physical Implementation Engineer to drive the physical implementation of advanced high-bandwidth memory system-on-chip designs. You will work collaboratively with design, verification, and manufacturing teams to ensure optimal performance and power efficiency.

The ideal candidate has a Bachelor’s or Master’s degree in Electrical Engineering and hands-on experience with EDA tools like Innovus and Calibre. Competitive benefits and a commitment to equal opportunity employment are also offered.

Qualifications

• Hands-on experience with industry electronic design automation tools such as Innovus, Fusion Compiler, IC Validator, or Calibre for physical design and signoff.
• Solid understanding of static timing analysis fundamentals and clocking concepts.
• Working knowledge of power intent methodologies including UPF or CPF.

Responsibilities

• Support physical implementation of SoC blocks from floorplanning through optimization.
• Assist with timing closure across multi-mode scenarios using PrimeTime or Tempus.
• Collaborate with RTL design and integration teams to ensure correct implementations.

Skills

Hands-on experience with EDA tools

Understanding of static timing analysis

Familiarity with physical verification

Experience with HBM or DRAM designs

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Innovus

Fusion Compiler

IC Validator

Calibre

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

You will drive physical implementation of advanced high‑bandwidth memory (HBM) system‑on‑chip (SoC) logic and base die designs from netlist through GDSII within the Heterogeneous Integration Group.

You will collaborate closely with design, verification, design for test (DFT), packaging, and manufacturing teams to deliver best‑in‑class performance, power, and area (PPA) with robust signoff collateral.

This is a hands‑on role where you can own blocks or top‑level integration across multiple product generations and see your work through tapeout and silicon.

Responsibilities

• Support physical implementation of SoC blocks from floorplanning through placement, clock tree synthesis (CTS), routing, and optimization to meet performance, power, and area targets.
• Assist with setup and hold timing closure across multi‑mode, multi‑corner (MMMC) scenarios using industry tools such as PrimeTime or Tempus under guidance of senior engineers.
• Collaborate with RTL design and integration teams to ensure correct clocking, reset strategies, and power intent implementation throughout the design.
• Integrate and implement complex intellectual property (IP) blocks including controllers, interfaces, memory built‑in self‑test (MBIST), design for test (DFT) logic, buffers, and PHY‑adjacent logic with focus on timing and physical correctness.
• Run and debug physical signoff checks such as design rule checking (DRC), layout versus schematic (LVS), and timing signoff, addressing violations with support from signoff experts.
• Work with DFT teams to ensure scan and MBIST logic are physically clean and do not negatively impact timing, congestion, or routability.
• Participate in tapeout readiness activities including engineering change order (ECO) flows, checklists, design reviews, and post‑silicon debug by correlating silicon behavior with physical design, static timing analysis, and power analysis.
• Apply hands‑on experience with electronic design automation tools and methodologies while working effectively in a cross‑functional, global team environment.

Minimum Qualifications

• Hands‑on experience with industry electronic design automation tools such as Innovus, Fusion Compiler, IC Validator (ICV), or Calibre for physical design and signoff.
• Solid understanding of static timing analysis fundamentals, clocking concepts, and Synopsys Design Constraints (SDC).
• Working knowledge of power intent methodologies including Unified Power Format (UPF) or Common Power Format (CPF), power grid planning, and basic power integrity considerations.
• Familiarity with physical verification and signoff flows including design rule checking, layout versus schematic, and parasitic awareness.
• Experience with hierarchical physical design and system‑on‑chip integration methodologies.

Preferred Qualifications

• Experience with HBM or dynamic random‑access memory (DRAM) adjacent SoC designs or memory‑subsystem‑heavy SoCs.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Minimum three to five years of experience in a related physical design or SoC implementation role.
• Experience with signal integrity and reliability analysis including IR drop and electromigration using tools such as Ansys.
• Experience developing or using Tcl or Python scripts to automate physical design checks, reporting, and flow improvements.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. Micron offers a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.