Hardware Security Tech Leader — Hybrid in Raleigh

Cisco Systems, Inc.; Clegg (NC); Hybrid; USD 139,000 - 201,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Paid time away and generous vacation

RSU grants eligibility

Job summary

Cisco Systems, Inc. seeks a hardware security leader to own security requirements and design guidance across product teams and firmware/hardware groups in a hybrid Raleigh, NC environment.

You will mentor engineers and drive security across complex platforms from system-level architecture to silicon level. Focus areas include RoT, secure boot, cryptographic acceleration, and cross-functional collaboration with Open Compute and SONiC groups.

Qualifications

• Degree in Electrical/Computer Engineering; 9+ years experience (BS), 6+ years (MS), or 3+ years (PhD).
• Experience leading security initiatives and mentoring engineers as a technical leader.
• Background in hardware development (reading schematics, block diagrams, datasheets) and security.

Responsibilities

• Provide security requirements and architectural design guidance to product teams and hardware design engineers.
• Coordinate with external groups like OCP and SONiC Security Working Groups.
• Evaluate hardware designs and datasheets to identify threats and compliance gaps.
• Apply industry standards like NIST SP 800-193, CNSA 2.0, EU CRA to hardware security requirements.
• Author security requirements, review checklists, threat models, and engineering specifications.
• Lead multiple concurrent security evaluations and design reviews across programs.

Skills

Security leadership

Mentoring engineers

Hardware design

System-level analysis

Education

Electrical/Computer Engineering

Job description

Cisco Systems, Inc. seeks a hardware security leader to own security requirements and design guidance across product teams and firmware/hardware groups in a hybrid Raleigh, NC environment.

You will mentor engineers and drive security across complex platforms from system-level architecture to silicon level. Focus areas include RoT, secure boot, cryptographic acceleration, and cross-functional collaboration with Open Compute and SONiC groups.