Hardware Design Verification Co-op Intern — AI ASIC

Advanced Micro Devices, Inc.; San Jose (CA); Hybrid; USD 28.000 - 41.000; Vollzeit

Zusammenfassung

Advanced Micro Devices, Inc. (AMD) seeks a Hardware Design Verification intern/co-op for its San Jose/Santa Clara program.

The role targets full-time work in hybrid or onsite settings during the internship period, with Spring/Summer and Summer/Fall windows outlined for 2027. You will collaborate with senior engineers on verification plans, build models, write test scripts in Python/Perl, and support regression and debugging efforts across Verilog/SystemVerilog hardware blocks.

Qualifikationen

• Enrollment in a US-based university for a Master's degree in Electrical or Computer Engineering or related field.
• Familiarity with C/C++/Python/Perl/Shell/UVM.
• Experience with Verilog or SystemVerilog.
• Understanding of digital systems and computer organization.
• Experience with Linux/Unix/Windows development environments.
• Hands-on hardware lab experience with test equipment.

Aufgaben

• Collaborate with senior engineers to build verification tests and models.
• Develop scripts to manage compute resources with Python/Perl.
• Support test regression flows for project development.
• Review tools and processes to improve simulation performance.
• Assist debugging of test cases and hardware/software integration.
• Build test platforms and perform system-level testing.
• Validate production readiness of hardware and software features.
• Identify root causes through debugging and measurement.

Kenntnisse

C++

Python

C

Perl

Shell

UVM

Verilog

SystemVerilog

Digital systems

PC building

Linux

Unix

Windows

Logic design

Transistor behavior

Oscilloscopes

Multimeters

Ausbildung

Master's program in Electrical/Computer Engineering

Jobbeschreibung

Advanced Micro Devices, Inc. (AMD) seeks a Hardware Design Verification intern/co-op for its San Jose/Santa Clara program.

The role targets full-time work in hybrid or onsite settings during the internship period, with Spring/Summer and Summer/Fall windows outlined for 2027. You will collaborate with senior engineers on verification plans, build models, write test scripts in Python/Perl, and support regression and debugging efforts across Verilog/SystemVerilog hardware blocks.