Hardware Design Engineer 1

Managed Staffing; Santa Clara (CA); On-site; USD 110,000 - 170,000; Full time

Job summary

Managed Staffing, Inc. is seeking a Physical Design Engineer to take RTL to GDS with automated synthesis, place and route, and timing verification in a fast-paced environment in Santa Clara, CA.

You will work on high-speed SerDes PHY designs, contribute to floorplanning, IP integration, and design checks to ensure timing, power, and area targets are met, collaborating with geographically distributed teams.

Qualifications

• 2-5+ years working experience in high-speed SerDes PHY designs or other high-performance IP designs.
• Proficiency in Python and/or Perl; additional languages are a plus.
• Experience with automated design flows for RTL synthesis and timing-driven PnR.
• Experience in automated flows for clock tree synthesis, gating, buffer insertion, scan stitching.
• Strong background in digital circuit techniques for high-speed, low-power designs.
• Experience in floor planning and IP integration; final sign-off for large IP.

Responsibilities

• Automated synthesis and timing-driven PNR of RTL blocks for high-speed datapath and control logic.
• Design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching.
• Support floor planning, IP integration, checks for logic equivalence and electrical quality.
• Provide final sign-off for large IP delivery.

Skills

Physical design

RTL to GDS

Synthesis

Place & Route

Timing analysis

Floorplanning

IP integration

Verilog

Python

Perl

Education

Master’s degree in EE/CS

Bachelor’s degree in EE/CS

Tools

Layout tools

Schematic tools

Job description

THE ROLE:

This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification

THE PERSON:

Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams

RESPONSIBILTIES:

This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED SKILLED SETS:

• 2-5+ years working experience, preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs
• Proficiency in Python and/or Perl is required. Additional languages are a plus.
• Versatility with scripts to automate design flow, and quality checks.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation

EDUCATION:

Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.