GPU Formal Verification Engineer: Property & Datapath

Canvendor; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Canvendor seeks a Formal Design Verification Engineer to craft formal constraints, checks, and coverage for sequential equivalence in clock gating logic and datapath verification against C and RTL models.

You will diagnose formal failures, partner with RTL designers, and push verification setup improvements in a GPU-rich design environment with memory hierarchies and complex math units.

Qualifications

• BSEE, CS/CE degree with 3+ years experience; advanced degrees preferred.
• Strong understanding of CPU/GPU design architecture.
• Solid SystemVerilog (SV) and SystemVerilog Assertion (SVA) coding skills.
• Experience developing formal verification setups is essential.
• Experience with constrained random testbenches is a plus.
• Familiarity with formal tools: VC Formal, Jasper Gold, Questa Formal.

Responsibilities

• Develop formal verification setup using SystemVerilog modules and Assertions.
• Run formal verification checks, analyze results, and debug issues.
• Develop and enhance constraints, checks, and cover points for quality.
• Verify GPU design blocks using formal methods like sequential equivalence checking.
• Datapath verification using C models and formal property verification.
• Contribute to reduction techniques, convergence, and proof depth.
• Collaborate with design, architecture, and software teams to align verification goals.
• Document test plans, convergence reports, and results.

Skills

SystemVerilog

SVA

Formal verification

Linux

C models

Education

BSEE, Computer Engineering, or Computer Science bachelor's degree

Masters or Ph.D. degree preferred

Tools

VC Formal

Jasper Gold

Questa Formal

Job description

Canvendor seeks a Formal Design Verification Engineer to craft formal constraints, checks, and coverage for sequential equivalence in clock gating logic and datapath verification against C and RTL models.

You will diagnose formal failures, partner with RTL designers, and push verification setup improvements in a GPU-rich design environment with memory hierarchies and complex math units.