Senior GPU Formal Verification Engineer - Equity Eligible

NVIDIA Corporation; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Formal Verification Engineer in Santa Clara, CA to verify GPU micro-architectures using formal methods. You will define verification scope, write testplans, and drive bounded/full proofs with RTL, collaborating across distributed teams and with pre/post-silicon verification groups.

The role requires 5+ years in CS/CE/EE/Math and strong scripting. Candidates should have Verilog/SystemVerilog experience, formal tools expertise, and the ability to communicate complex

Qualifications

• 5+ years of experience in formal verification for GPUs/CPUs.
• Proficient in Verilog/SystemVerilog and RTL comprehension.
• Experience with formal verification methodologies and abstraction techniques.
• Strong scripting skills (Python/Perl/TCL) and good communication.

Responsibilities

• Identify key verification behaviors and write test plans for complex designs.
• Implement test plans using formal techniques and develop environment assumptions, assertions, and coverage properties.
• Develop abstraction models to manage complexity and achieve full or bounded proofs.
• Drive formal tools to maximize performance and efficiency.
• Debug RTL to diagnose failure scenarios and contribute to flows and scripts.
• Collaborate with architects, designers, and verification teams across locations.
• Communicate formal verification coverage clearly to partners.

Skills

Verilog / SystemVerilog

Formal verification

Scripting (Python/Perl/TCL)

RTL debugging

Team collaboration

Education

BS/MS/PhD in CS/CE/EE/Math

Tools

Formal verification tools

Job description

NVIDIA is seeking a Senior Formal Verification Engineer in Santa Clara, CA to verify GPU micro-architectures using formal methods. You will define verification scope, write testplans, and drive bounded/full proofs with RTL, collaborating across distributed teams and with pre/post-silicon verification groups.

The role requires 5+ years in CS/CE/EE/Math and strong scripting. Candidates should have Verilog/SystemVerilog experience, formal tools expertise, and the ability to communicate complex