Formal Design Verification Engineer

Saige Partners LLC; San Jose (CA); Presencial; USD 83.000 - 131.000; Jornada completa

Descripción de la vacante

Saige Partners LLC is seeking a Formal Design Verification Engineer in San Jose to develop formal verification environments for advanced GPU design blocks. You will create formal constraints, assertions, checks, and cover properties, and perform sequential equivalence checks and datapath verification between C and RTL models.

The role emphasizes collaboration with RTL designers, debugging formal failures, and improving verification methodologies within a dynamic engineering team.

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of relevant engineering experience.
• Strong understanding of CPU and/or GPU design architecture.
• Hands-on experience developing formal verification environments and setups.
• Proficient in SystemVerilog and SystemVerilog Assertions (SVA).
• Proficient in Linux environments and debugging verifications.
• Excellent written and verbal communication skills.

Responsabilidades

• Develop formal verification environments using SystemVerilog modules and SVA.
• Execute formal verification checks, analyze results, and debug failures.
• Develop and enhance formal constraints, assertions, checks, and cover properties.
• Verify GPU design blocks using formal methodologies including sequential equivalence checking.
• Perform datapath verification between C and RTL models.
• Develop and maintain formal verification environments for design features.
• Conduct proof-depth, complexity, and convergence analyses.
• Collaborate with RTL designers to troubleshoot failures and improve setups.
• Plan and manage verification activities with project teams and tools.
• Document test plans, convergence reports, and verification results.

Conocimientos

SystemVerilog

SystemVerilog Assertions

Linux

CPU/GPU architecture

Cross-functional collaboration

Educación

Bachelors in EE/CE/CS

Herramientas

Synopsys VC Formal

Cadence JasperGold

Siemens Questa Formal

Descripción del empleo

Position: Formal Design Verification Engineer (San Jose, CA)

Job Overview: We are seeking a Formal Design Verification Engineer to support advanced GPU design and verification initiatives. In this role, you will develop and implement formal verification strategies to ensure the functional correctness and reliability of complex GPU design blocks. You will be responsible for developing formal constraints, assertions, checks, and cover properties for new and existing design blocks. Your work will focus on sequential equivalence verification of clock-gating logic, property-based feature verification, and datapath equivalence verification between C and RTL models. The ideal candidate has hands‑on experience developing formal verification environments, analyzing proof convergence, debugging formal failures, and collaborating closely with RTL designers to resolve design and verification challenges. GPU architecture presents exciting technical challenges across memory hierarchies, parallel processing units, and complex mathematical operations. This is an excellent opportunity to work alongside a talented engineering team, gain exposure to cutting‑edge design and verification methodologies, and make a meaningful impact on next‑generation GPU products. This is a contract role.

Key Responsibilities

• Develop formal verification environments using SystemVerilog modules and SystemVerilog Assertions (SVA).
• Execute formal verification checks, analyze results, and debug failures to ensure design functionality and correctness.
• Develop and enhance formal constraints, assertions, checks, and cover properties to improve verification quality and coverage.
• Verify GPU design blocks using formal methodologies, including:
  • Sequential equivalence checking.
  • Property-based feature verification.
  • Datapath equivalence verification using C and RTL models.
• Develop formal-based datapath verification environments using RTL and C models.
• Develop and maintain property-based formal verification environments for design features.
• Perform proof-depth, complexity, and convergence analysis to evaluate formal verification effectiveness.
• Identify root causes of formal failures and determine whether issues originate from the design, constraints, or verification setup.
• Apply formal convergence techniques, including abstraction, black-boxing, and design reductions
• Collaborate with RTL designers to troubleshoot failures and improve formal setups or RTL implementation.
• Partner with cross-functional teams, including design, architecture, and software engineering, to align verification activities with project goals and requirements.
• Contribute to the development and continuous improvement of verification methodologies, tools, and workflows.
• Manage project execution and planning activities using tools such as Confluence and JIRA.
• Develop and maintain formal verification documentation, including test plans, convergence reports, complexity analysis reports, and verification results.
• Drive assigned formal verification activities and communicate progress, results, and potential challenges to project verification leads.

Qualifications

Required

• Bachelor's degree in Electrical Engineering (BSEE), Computer Engineering, Computer Science, or a related technical discipline.
• Minimum of 3+ years of relevant engineering experience.
• Strong understanding of CPU and/or GPU design architecture.
• Strong experience with SystemVerilog (SV) and SystemVerilog Assertions (SVA) development.
• Demonstrated hands-on experience developing formal verification environments and setups.
• Experience analyzing formal verification results, debugging failures, and improving proof convergence.
• Proficiency working in a Linux environment.
• Excellent written and verbal communication skills.
• Ability to collaborate effectively with cross-functional engineering teams.

Preferred

• Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience developing constrained-random testbenches.
• Experience with formal verification tools such as:
  • Synopsys VC Formal
  • Cadence JasperGold
  • Siemens Questa Formal
• Hands‑on experience with formal datapath verification using C and RTL models.
• Experience with sequential equivalence checking and property-based verification.
• Strong understanding of formal convergence techniques, proof‑depth analysis, abstraction, black-boxing, and design reduction methodologies.
• Experience working with project management and collaboration tools such as JIRA and Confluence.