GPU Formal Verification Engineer (Contract)

Protingent

San Jose (CA)

On-site

USD 117,000 - 131,000

Full time

7 days ago
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Job summary

Protingent Staffing is seeking a Contract GPU Formal Design Verification Engineer in San Jose, CA. You will develop formal constraints, checks, and cover points to verify sequential equivalence for clock gating and datapath verification using C models.

You will diagnose formal failures and collaborate with RTL designers to refine RTL or formal test setups. You will work with cross-functional teams to advance verification methodologies and document convergence reports and results.

Qualifications

  • BSEE/CE/CS degree and 3+ years in verification.
  • SV/SVA coding experience is required.
  • Experience with formal tools VC Formal, Jasper Gold or Questa Formal.
  • Linux environment experience and strong communication skills.

Responsibilities

  • Develop formal verification setup using System Verilog modules and Assertions.
  • Run formal verification checks, analyze results, and debug issues.
  • Develop and enhance constraints, checks, and cover points to ensure verification quality.
  • Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
  • Hands-on experience in developing formal-based datapath verification setups using RTL & C models.
  • Hands-on experience in developing formal property-based feature verification setups.
  • Analyze and deploy formal convergence techniques like abstraction and design reductions.
  • Collaborate with design, architecture, and software teams to align verification with project goals.

Education

BSEE / Computer Engineering / Computer Science
Masters or Ph.D. preferred

Tools

VC Formal
Jasper Gold
Questa Formal

Job description

Protingent Staffing is seeking a Contract GPU Formal Design Verification Engineer in San Jose, CA. You will develop formal constraints, checks, and cover points to verify sequential equivalence for clock gating and datapath verification using C models.

You will diagnose formal failures and collaborate with RTL designers to refine RTL or formal test setups. You will work with cross-functional teams to advance verification methodologies and document convergence reports and results.

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