GPU Formal Verification Engineer (Contract)

Saige Partners LLC; San Jose (CA); On-site; USD 83,000 - 131,000; Full time

Job summary

Saige Partners LLC is seeking a Formal Design Verification Engineer in San Jose to develop formal verification environments for advanced GPU design blocks. You will create formal constraints, assertions, checks, and cover properties, and perform sequential equivalence checks and datapath verification between C and RTL models.

The role emphasizes collaboration with RTL designers, debugging formal failures, and improving verification methodologies within a dynamic engineering team.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 3+ years of relevant engineering experience.
• Strong understanding of CPU and/or GPU design architecture.
• Hands-on experience developing formal verification environments and setups.
• Proficient in SystemVerilog and SystemVerilog Assertions (SVA).
• Proficient in Linux environments and debugging verifications.
• Excellent written and verbal communication skills.

Responsibilities

• Develop formal verification environments using SystemVerilog modules and SVA.
• Execute formal verification checks, analyze results, and debug failures.
• Develop and enhance formal constraints, assertions, checks, and cover properties.
• Verify GPU design blocks using formal methodologies including sequential equivalence checking.
• Perform datapath verification between C and RTL models.
• Develop and maintain formal verification environments for design features.
• Conduct proof-depth, complexity, and convergence analyses.
• Collaborate with RTL designers to troubleshoot failures and improve setups.
• Plan and manage verification activities with project teams and tools.
• Document test plans, convergence reports, and verification results.

Skills

SystemVerilog

SystemVerilog Assertions

Linux

CPU/GPU architecture

Cross-functional collaboration

Education

Bachelors in EE/CE/CS

Tools

Synopsys VC Formal

Cadence JasperGold

Siemens Questa Formal

Job description

Saige Partners LLC is seeking a Formal Design Verification Engineer in San Jose to develop formal verification environments for advanced GPU design blocks. You will create formal constraints, assertions, checks, and cover properties, and perform sequential equivalence checks and datapath verification between C and RTL models.

The role emphasizes collaboration with RTL designers, debugging formal failures, and improving verification methodologies within a dynamic engineering team.