Formal Verification Engineer: Prove Hardware Correctness

NVIDIA; Santa Clara (CA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking sharp, curious, and motivated students who are passionate about formal verification, digital design, and computer architecture. In this role, you will help verify advanced processor and accelerator designs using mathematical reasoning, assertions, model checking, and formal verification tools.

You will work with experienced formal verification engineers, architects, and RTL designers to understand design intent, identify important behaviors, write assertions and assumptions,

Qualifications

• BS/MS/Ph.D. or equivalent in CS/CE/EE/Mathematics
• Strong analytical and collaboration skills
• Familiarity with Verilog and SystemVerilog
• Programming or scripting in Python, Tcl, Perl, C/C++, or similar
• Ability to learn quickly and collaborate effectively

Responsibilities

• Learn and apply formal verification techniques to processor and accelerator designs
• Understand design behavior from specifications, RTL, and discussions with design teams
• Write assumptions, assertions, and cover properties to verify microarchitectural behavior
• Debug formal failures and counterexamples to identify RTL bugs or constraint issues
• Use abstraction, modeling, and scripting to improve proof convergence
• Communicate verification progress, coverage, risks, and findings

Skills

Analytical thinking

Collaboration

Learning quickly

Problem solving

Verilog knowledge

SystemVerilog knowledge

Python scripting

Tcl scripting

C/C++

Education

BS/MS/PhD in CS/CE/EE/Math

Tools

Verilog

SystemVerilog

Job description

NVIDIA is seeking sharp, curious, and motivated students who are passionate about formal verification, digital design, and computer architecture. In this role, you will help verify advanced processor and accelerator designs using mathematical reasoning, assertions, model checking, and formal verification tools.

You will work with experienced formal verification engineers, architects, and RTL designers to understand design intent, identify important behaviors, write assertions and assumptions,