GPU Formal Design Verification

Protingent; San Jose (CA); On-site; USD 117,000 - 131,000; Full time

Job summary

Protingent Staffing is seeking a Contract GPU Formal Design Verification Engineer in San Jose, CA. You will develop formal constraints, checks, and cover points to verify sequential equivalence for clock gating and datapath verification using C models.

You will diagnose formal failures and collaborate with RTL designers to refine RTL or formal test setups. You will work with cross-functional teams to advance verification methodologies and document convergence reports and results.

Qualifications

• BSEE/CE/CS degree and 3+ years in verification.
• SV/SVA coding experience is required.
• Experience with formal tools VC Formal, Jasper Gold or Questa Formal.
• Linux environment experience and strong communication skills.

Responsibilities

• Develop formal verification setup using System Verilog modules and Assertions.
• Run formal verification checks, analyze results, and debug issues.
• Develop and enhance constraints, checks, and cover points to ensure verification quality.
• Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
• Hands-on experience in developing formal-based datapath verification setups using RTL & C models.
• Hands-on experience in developing formal property-based feature verification setups.
• Analyze and deploy formal convergence techniques like abstraction and design reductions.
• Collaborate with design, architecture, and software teams to align verification with project goals.

Education

BSEE / Computer Engineering / Computer Science

Masters or Ph.D. preferred

Tools

VC Formal

Jasper Gold

Questa Formal

Job description

Job Title: GPU Formal Design Verification Position

Job Description

Protingent Staffing has an exciting contract GPU Formal Design Verification with our client located in San Jose, CA. As a Contract - Formal Design Verification Engineer, you will be responsible for developing formal constraints, checks, and cover properties to new and existing design blocks towards verifying sequential equivalence for clock gating logic & so, verifying design features using assertions and verifying datapath equivalence of C and RTL models. You will diagnose formal failures and work closely with RTL designers to update formal setup or RTL code. GPU designs provide a wealth of technical challenges in memory hierarchy, parallel processing units, and complex mathematical units. This is a challenging and rewarding position where you will learn cutting-edge design and verification techniques from an exceptionally talented team, and where your contributions will make a visible impact to the end product.

Job Responsibilities

• Develop formal verification setup using System Verilog modules and Assertions
• Run formal verification checks, analyze the results, and debug any issues.
• Develop and enhance constraints, checks, and cover points to achieve verification quality.
• Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
• Hands-on experience in developing formal based datapath verification setups using RTL & C Models
• Hands-on experience in developing formal property-based feature verification setups
• In-depth expertise on proof depth and convergence analysis for formal setups
• Root cause formal failures to identify design or test setup issues.
• Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions.
• Work closely with cross-functional teams, including design, architecture, and software teams, to ensure that verification efforts are aligned with project goals and requirements.
• Participate in the development and improvement of verification methodologies, tools, and flows to increase efficiency and effectiveness of verification efforts.
• Adhere to project execution and planning approaches using Confluence, JIRA and relevant techniques.
• Create and maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results.
• Responsible in driving formal verification tasks & report to project verification leads as required.

Job Qualifications

• BSEE, Computer Engineering, or Computer Science bachelor’s degree and a minimum of 3+ years of experience
• Masters or Ph.D. degree preferred
• Good understanding of CPU and/or GPU design architecture
• Strong experience or exposure to System Verilog (SV) and System Verilog Assertion (SVA) coding skills is required
• Experience in developing formal verification setups is a must
• Experience in developing constrained random testbenches is preferred
• Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal
• Experience working in a Linux environment
• Excellent communication skills and be able to work with cross-functional teams to execute verification plan.

Job Details

Job type: Contract Pay Rate: $85- $95/hr. Location: San Jose, CA.

Benefits Package: Protingent offers

• competitive salaries
• insurance plan options (HDHP plan or POS plan)
• education/certification reimbursement
• pre-tax commuter benefits
• Paid Time Off (PTO)
• an administered 401k plan

About Protingent

Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation — from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We’re passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.