Pre-Silicon Modeling Leader: FPGA Architecture & Simulation

191 Altera Corporation

San Jose (CA)

On-site

USD 232,000 - 341,000

Full time

3 days ago
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Job summary

Altera seeks a Product Architecture Model Development Leader to drive behavioral and architectural models for next-generation FPGA silicon before RTL development.

You will lead a team, define modeling standards, and ensure models serve as a single source of truth for architecture, verification, RTL, and software teams.

The role involves coordinating with silicon architects, verifying teams, and enabling early customer prototyping and pathfinding across multiple silicon generations.

Qualifications

  • Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.
  • 15+ years of experience in silicon architecture, design, or verification with 5+ years in leadership.
  • Strong hands-on experience developing behavioral/functional/performance models in C++, SystemC, and/or SystemVerilog.
  • Deep understanding of FPGA/ASIC architecture Fundamentals.

Responsibilities

  • Lead a team of behavioral modeling engineers for cycle-approximate and functional models of FPGA architecture.
  • Define modeling methodology, coding standards, and architecture for models used in pre-silicon design flow.
  • Own the roadmap for model development in lockstep with architecture milestones.

Skills

C++
SystemC
SystemVerilog
Python
Leadership
FPGA architecture

Education

Bachelor's degree in CE/EE/CS
Master's or PhD preferred

Tools

SystemVerilog
SystemC
Python
C++

Job description

Altera seeks a Product Architecture Model Development Leader to drive behavioral and architectural models for next-generation FPGA silicon before RTL development.

You will lead a team, define modeling standards, and ensure models serve as a single source of truth for architecture, verification, RTL, and software teams.

The role involves coordinating with silicon architects, verifying teams, and enabling early customer prototyping and pathfinding across multiple silicon generations.

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