Senior FPGA Engineer – RTL, Timing & Production

Talentify; Newtown (PA); Hybrid; USD 76,000 - 92,000; Full time

Benefits offered by this job

Medical benefits

401(k) retirement

Life Insurance

PTO

Transportation benefits

Employee Assistance Program

Job summary

Actalent is seeking an FPGA Engineer for RTL design and FPGA development to support product lifecycles from design to deployment.

The role emphasizes timing closure, simulation, and verification with a strong emphasis on hands-on RTL coding. Collaboration with hardware, embedded software, and test engineers is essential, and experience with Xilinx, Microchip, or Intel/Altera is valued.

Qualifications

• 7–10 years in RTL/FPGA design and product development.
• Hands-on FPGA coding with VHDL (preferred) or Verilog.
• Experience with timing closure, simulation, and verification.

Responsibilities

• Design and develop FPGA-based products with RTL focus.
• Collaborate with hardware, firmware, and test teams.
• Perform simulation and verification prior to hardware deployment.
• Achieve timing closure on high-speed FPGA designs.
• Provide lab debugging and product development support.

Skills

RTL design

FPGA development

Simulation

Verification

Timing analysis

Lab debugging

Python scripting

TCL scripting

VHDL

Verilog

Tools

Xilinx FPGA

Microchip

Intel/Altera

Job description

Actalent is seeking an FPGA Engineer for RTL design and FPGA development to support product lifecycles from design to deployment.

The role emphasizes timing closure, simulation, and verification with a strong emphasis on hands-on RTL coding. Collaboration with hardware, embedded software, and test engineers is essential, and experience with Xilinx, Microchip, or Intel/Altera is valued.