SoC Static Timing Engineer – Signoff, Clock, Jitter Focus

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google in Mountain View is seeking a senior SoC STA engineer to deliver timing analysis for complex chips. You will define timing signoff, clock tree jitter, and signoff checklists, collaborating across RTL, PnR, and verification teams to optimize energy, performance, and area.

The role emphasizes working with PrimeTime/Tempus and delivering silicon milestones on aggressive schedules. Qualifications include a strong background in electrical engineering or CS, extensive STA experience, and

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Responsibilities

• Deliver system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs.

Skills

Silicon timing closure

Static timing tools

STA signoff

Silicon delivery

Education

Bachelor's degree in Electrical Engineering or Computer Science

Master's degree (preferred)

Tools

PrimeTime

Tempus

Job description

Google in Mountain View is seeking a senior SoC STA engineer to deliver timing analysis for complex chips. You will define timing signoff, clock tree jitter, and signoff checklists, collaborating across RTL, PnR, and verification teams to optimize energy, performance, and area.

The role emphasizes working with PrimeTime/Tempus and delivering silicon milestones on aggressive schedules. Qualifications include a strong background in electrical engineering or CS, extensive STA experience, and