Frontier AI Physical Design Engineer

Etched; San Jose (CA); On-site; USD 190,000 - 270,000; Full time

Benefits offered by this job

Medical, dental, and vision

Housing subsidy

Relocation support

Wellness benefits

Daily lunch and dinner

Unlimited compute budget

Job summary

Etched is building a new category of AI hardware focused on frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—from floorplanning to GDSII completion—and drive PPA optimization and timing closure.

You’ll collaborate with RTL designers to iterate rapidly and bring products to market. You will lead PV optimization across DRC/LVS/ERC, manage timing constraints, and push for successful tapeouts with a repeatable methodology.

Qualifications

• 10+ years of chip planning, top level PD, floorplanning experience.
• Experience with top-level and full-chip closure on advanced process nodes (5nm and below).
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows.
• Experience with Synopsys PrimeTime and Cadence Tempus for timing signoff.
• Experience with Pegasus or Calibre for physical verification signoff.
• Experience with hierarchical timing budgeting, constraint management, and ECO closure.
• Experience with Cadence Innovus for top-level assembly, routing, and layout fixes.
• Deeply creative and able to think from first principles.

Responsibilities

• Own full-chip clocking across all PVT corners and modes.
• Manage MMMC timing closure at the top level.
• Own timing constraints and hierarchical timing budgeting between top level and blocks.
• Drive functional and timing ECO closure and achieve final timing signoff for tapeout.
• Own end-to-end physical verification closure at block, sub-system, and full-chip level across DRC, LVS, ERC, antenna, density, fill, and top-level integration.
• Debug complex PV violations across layout, routing, macros, IP, power grid, rule decks, and tool or setup issues, and fix violations directly in layout using Innovus.
• Build a repeatable, tapeout-ready PV methodology with clean runs, waiver discipline, version control, triage, and final signoff reviews.

Skills

chip planning

top-level PD

floorplanning

timing closure

PV methods

Dynamiс PV tools

Innovus

Genus

Fusion Compiler

PrimeTime

Python scripting

ML/LLM familiarity

Tools

Cadence Innovus

Cadence Genus

Synopsys Fusion Compiler

Synopsys PrimeTime

Cadence Tempus

Pegasus

Calibre

Job description

Etched is building a new category of AI hardware focused on frontier inference clusters. As a top-level PD engineer, you will own full-chip implementation—from floorplanning to GDSII completion—and drive PPA optimization and timing closure.

You’ll collaborate with RTL designers to iterate rapidly and bring products to market. You will lead PV optimization across DRC/LVS/ERC, manage timing constraints, and push for successful tapeouts with a repeatable methodology.