Frontier AI Hardware: Block-Level Physical Design Engineer

The Consensus; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

$500 per month credit for waiving med

Housing subsidy of $2k per month near

Relocation support to San Jose

Wellness benefits

Daily lunch and dinner in office

Unlimited compute budget

Job summary

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off and drive Block-level PPA optimization, collaborating closely with RTL designers to iterate rapidly and bring our products to market.

You will lead floorplanning, placement, clock tree synthesis, routing, timing closure, and sign-off across EM, IR drop, RC extraction, and antenna analysis, while supervising

Qualifications

• 5-10+ years of previous experience with PD.
• Tools, flow, and design methodology from RTL synthesis to GDSII sign-off.
• Experience with back-end design and timing closure on 5nm and below.
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows.
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
• Scripting ability in Tcl, Python, or Perl for flow automation and debug
• Deeply creative and able to think from first principles

Responsibilities

• Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
• Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
• Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
• Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.
• Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
• Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.
• Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.

Skills

Block-level PD

Floorplanning

Placement & Routing

Synthesis/STA

Timing closure

Power integrity

Scripting (Python/Tcl)

Team collaboration

Tools

Cadence Innovus

Cadence Genus

Synopsys Fusion Compiler

PrimeTime

Tempus

Voltus

Job description

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off and drive Block-level PPA optimization, collaborating closely with RTL designers to iterate rapidly and bring our products to market.

You will lead floorplanning, placement, clock tree synthesis, routing, timing closure, and sign-off across EM, IR drop, RC extraction, and antenna analysis, while supervising