Physical Design Engineer

The Consensus; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, and vision

Lunch provided daily

Unlimited compute budget

Job summary

Etched, based in Austin, TX, is seeking exceptional Physical Design engineers to own block-level implementation and verification, drive timing closure and PPA, and supervise third-party PD work. The role collaborates with RTL designers to refine PD flows and improve CAD infrastructure.

You will be responsible for PD flows, dashboards, and block-level closure while partnering with teams across RTL and EDA vendors. Expect exchange with the San Jose team as needed.

Qualifications

• 5–10+ years of PD experience.
• RTL to GDSII sign-off knowledge.
• Back-end design and timing closure on 5nm and below.
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.).
• Familiar with UPF-based low power design, ATPG, formal verification, floorplanning, placement, CTS, routing, EM/antenna analysis.

Responsibilities

• Run PD flows to close blocks and support ASIC infrastructure.
• Develop dashboards to track PD project convergence.
• Collaborate with RTL designers to improve PPA.
• Oversee outsourcing of PD to third-party services.
• Optimize tool flows and coordinate with EDA vendors.
• Own block-level closure accountability.

Skills

PD experience

Python scripting

ML awareness

Tools

Cadence Innovus

Cadence Genus

Synopsys ICC2

Fusion Compiler

PrimeTime

Tempus

Voltus

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.

Key Responsibilities

• Deeply understand what is involved in physical design
• Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
  improve CAD infrastructure
• Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
• Drive dashboards that show the convergence of projects related to PD
• Optimize tool flows, working with EDA vendors to incorporate the latest features
• Accountable for block level closure
• Supervise the outsourcing of physical design to a 3rd party service

You may be a good fit if you have

• 5-10+ years of previous experience with PD
• Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
• Experience with back-end design and timing closure on advanced process nodes (5nm
  and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
  automated RTL-to-GDSII flows
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
  routing, IR drop, and EM/antenna analysis
• Deeply creative and able to think from first principles

Strong candidates may also have experience with

• Familiarity with modern ML and LLM model architectures
• Ability to program with Python or another scripting language
• Familiarity with AI tools for programming/coding
• Startup experience or comfort working in fast-paced environments

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.