Frontier AI Physical Design Engineer: Block & Subsystem

Doist; San Jose (CA); On-site; USD 160,000 - 230,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Housing subsidy

Relocation support

Lunch in office

Unlimited compute budget

Job summary

Etched is building a new category of AI hardware focused on frontier inference clusters. We seek a Physical Design Engineer to own block-level implementation from synthesis through GDSII, driving timing and power in a fast-paced, in-person San Jose environment.

You will collaborate with RTL designers, optimize PPA, and supervise external crews to deliver high-quality blocks that integrate into the top-level design. This role emphasizes hands-on flow mastery and rapid iteration.

Qualifications

• 5+ years of physical design experience (PD) in semiconductor back-end flows.
• Experience with block-level implementation including floorplanning, placement, CTS, routing, and sign-off.
• Proficient in using P&R and sign-off tools for timing and power.
• Scripting ability in Tcl and Python for flow automation.
• Strong collaboration with RTL teams and feedback on PPA improvements.

Responsibilities

• Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
• Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
• Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
• Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.
• Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
• Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.
• Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.

Skills

Block-level PD

Timing closure

Scripting (Tcl/Python)

Floorplanning

RTL feedback to PD

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Cadence Innovus

Cadence Genus

Synopsys Fusion Compiler

PrimeTime

Tempus

Voltus

Job description

Etched is building a new category of AI hardware focused on frontier inference clusters. We seek a Physical Design Engineer to own block-level implementation from synthesis through GDSII, driving timing and power in a fast-paced, in-person San Jose environment.

You will collaborate with RTL designers, optimize PPA, and supervise external crews to deliver high-quality blocks that integrate into the top-level design. This role emphasizes hands-on flow mastery and rapid iteration.