Front-End Verification Engineer — SystemVerilog/UVM

AMD; San Jose (CA); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits

Hybrid work model

Equal opportunity employer

Job summary

AMD in San Jose, CA is seeking a Front-End Verification Engineer to validate the functional correctness of next-generation AMD/Xilinx devices. You will work across a multi-site global team, driving verification from feature definition through silicon readiness.

The role emphasizes collaboration, strong analytical skills, and ownership of complex verification challenges, with hands-on work in SystemVerilog/UVM, RTL debugging, and test bench development.

Qualifications

• Knowledge of Verilog, SystemVerilog and UVM is a must.
• Strong understanding of modern verification techniques and coverage metrics.
• Experience with gate-level verification and constrained-random testing is a plus.

Responsibilities

• Collaborate with architects, hardware and firmware engineers to understand the new features to be verified
• Take ownership of block level verification tasks
• Define test plans, test benches, and tests using System Verilog and UVM
• Debug RTL and gate simulations and work with HW/SW teams to verify fixes
• Review functional and code coverage metrics to meet coverage requirements
• Develop and improve existing verification flows and environments

Skills

SystemVerilog

UVM

Verilog

C/C++

Python

RTL debugging

Power/Reset verification

Assembly knowledge

Education

Bachelor's or Master's in Computer Engineering or Electrical Engineering

Tools

Verilog simulators

HDL verification tools

Simulation environments

Job description

AMD in San Jose, CA is seeking a Front-End Verification Engineer to validate the functional correctness of next-generation AMD/Xilinx devices. You will work across a multi-site global team, driving verification from feature definition through silicon readiness.

The role emphasizes collaboration, strong analytical skills, and ownership of complex verification challenges, with hands-on work in SystemVerilog/UVM, RTL debugging, and test bench development.