SystemVerilog/UVM Verification Engineer (Front-End)

Advanced Micro Devices; San Jose (CA); On-site; USD 95,000 - 120,000; Full time

Benefits offered by this job

Benefits offered as per AMD benefits at a glance.

Job summary

Advanced Micro Devices is seeking a Front-End Verification Engineer in San Jose, CA. You will validate the functionality of next-generation AMD/Xilinx devices by collaborating with cross-functional teams and driving verification execution from definition through silicon readiness.

The ideal candidate has strong skills in digital design and advanced verification techniques including System Verilog and UVM. Responsibilities include defining and owning test plans and verification tasks within a collaborative environment.

Qualifications

• Strong understanding of computer architecture and logic design.
• Knowledge of verification techniques, including assertion and metric-driven verification.
• Experience with gate level simulation and verification.

Responsibilities

• Collaborate with architects and engineers to define features for verification.
• Own block level verification tasks and define test plans.
• Debug RTL and gate simulations and ensure fixes are verified.
• Review functional and code coverage metrics to meet requirements.
• Develop and improve verification flows and environments.

Skills

Digital design

Verification methodologies

Analytical skills

Problem-solving skills

Education

Bachelor’s or Master’s degree in computer engineering, Electrical Engineering or related field

Tools

System Verilog

UVM

Verilog

C/C++

Python

Job description

Advanced Micro Devices is seeking a Front-End Verification Engineer in San Jose, CA. You will validate the functionality of next-generation AMD/Xilinx devices by collaborating with cross-functional teams and driving verification execution from definition through silicon readiness.

The ideal candidate has strong skills in digital design and advanced verification techniques including System Verilog and UVM. Responsibilities include defining and owning test plans and verification tasks within a collaborative environment.