Silicon Design Verification Engineer - UVM & SystemVerilog

AMD; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

AMD is seeking a Silicon Design Verification Engineer in San Jose, CA. You will work in the SOC Verification Team, designing testbenches in SystemVerilog and UVM, and creating robust verification environments for complex IP designs.

You will own block-level test benches, collaborate with RTL to optimize clock gating, and verify performance and power aspects using modern methodologies and tools. A Master’s degree is required, with expertise in SV, UVM, C++, and Python.

Qualifications

• Master's degree in computer engineering or electrical engineering.
• Strong knowledge of computer organization and digital logic fundamentals.
• Experience with SystemVerilog, C++, Python.
• Prior verification experience with UVM and formal tools is a plus.
• Familiarity with PCIe and AMBA AXI protocols.

Responsibilities

• Design testbenches in SystemVerilog and UVM to verify the design.
• Create test plans for complex IP designs with senior engineers.
• Develop constrained-random and directed verification environments.
• Debug tests with design engineers to achieve functional correctness of blocks.
• Coordinate with RTL engineers to improve verification coverage and clock gating.
• Monitor verification quality metrics like pass rates and coverage.

Skills

SystemVerilog

UVM

C++

Python

PCIe

AMBA AXI

Education

Master's degree in computer engineering/Electrical Engineering

Job description

AMD is seeking a Silicon Design Verification Engineer in San Jose, CA. You will work in the SOC Verification Team, designing testbenches in SystemVerilog and UVM, and creating robust verification environments for complex IP designs.

You will own block-level test benches, collaborate with RTL to optimize clock gating, and verify performance and power aspects using modern methodologies and tools. A Master’s degree is required, with expertise in SV, UVM, C++, and Python.