Front-End Design Director: RTL & IP Leadership

CADENCE US; Austin (TX); Presencial; USD 140.000 - 210.000; Jornada completa

Descripción de la vacante

Cadence Design Systems, Inc. in Austin, TX seeks an experienced Front End Design engineer to lead RTL design projects. You will mentor a team of RTL design engineers and drive microarchitectural features for IPs and subsystems, ensuring PPA goals are met.

The role requires hands-on RTL development in Verilog/SystemVerilog/VHDL and oversight of pre-silicon verification, including Lint, CDC, FV, and quality checks, with collaboration across DV, PD, architecture, and firmware teams.

Formación

• 10+ years of Front End design and/or verification in semiconductor industry.
• Experience in leading and managing complex engineering projects.
• Rich experience in IP creation and/or SoC and IP integration.
• Expert in RTL design (Verilog), simulators/debuggers.
• Hands on experience in Synthesis, SDC creation and support PD and STA teams.

Responsabilidades

• Technical Leadership: Guide and mentor a team of RTL design engineers.
• Design & Microarchitecture: Define and develop microarchitectural features for IPs and subsystems.
• RTL Development: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL.

Conocimientos

Front End design

RTL design

Leadership

SoC/IP integration

Verilog/SystemVerilog/VHDL

Synthesis/PD/STA

Educación

BS/MS Engineering or Computer Sciences

Herramientas

Cadence Front End Toolset

Simulators

Descripción del empleo

Cadence Design Systems, Inc. in Austin, TX seeks an experienced Front End Design engineer to lead RTL design projects. You will mentor a team of RTL design engineers and drive microarchitectural features for IPs and subsystems, ensuring PPA goals are met.

The role requires hands-on RTL development in Verilog/SystemVerilog/VHDL and oversight of pre-silicon verification, including Lint, CDC, FV, and quality checks, with collaboration across DV, PD, architecture, and firmware teams.