CPU RTL Design Lead — Front-End Architect (Equity)

Google Inc; Austin (TX); On-site; USD 240,000 - 333,000; Full time

Job summary

Google Austin, TX, USA is seeking engineers for front-end CPU design and microarchitecture work across high-performance silicon projects. You will contribute to RTL development using Verilog/SystemVerilog and work closely with verification, architecture, and software teams to reach aggressive performance and efficiency goals.

The role emphasizes collaboration across hardware teams, and requires deep expertise in digital logic, RTL design, and modern PPA-friendly methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 15 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF).

Responsibilities

• Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
• Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies.
• Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality.
• Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.
• Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort.

Skills

digital logic design

RTL design

Verilog

SystemVerilog

Lint

UPF

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree or PhD (preferred)

Job description

Google Austin, TX, USA is seeking engineers for front-end CPU design and microarchitecture work across high-performance silicon projects. You will contribute to RTL development using Verilog/SystemVerilog and work closely with verification, architecture, and software teams to reach aggressive performance and efficiency goals.

The role emphasizes collaboration across hardware teams, and requires deep expertise in digital logic, RTL design, and modern PPA-friendly methodologies.