FPGA Verification Engineer :: Santa Clara, CA

STI; Santa Clara (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

STI in Santa Clara, CA is seeking a skilled FPGA Verification Engineer to verify complex FPGA designs, develop verification plans, and work with design engineers to ensure quality and performance.

The role requires 3+ years in FPGA verification, strong SystemVerilog and UVM experience, and familiarity with QuestaSim or VCS. This on-site position emphasizes collaboration and rigorous debugging. A Bachelor's or Master's in EE or CE is required.

Qualifications

• Bachelor's or Master's in EE, CE, or related field.
• 3+ years FPGA verification experience.
• Proficiency in SystemVerilog and UVM.
• Experience with QuestaSim or VCS.
• Knowledge of code and functional coverage analysis.
• Strong debugging and problem-solving skills.
• Excellent communication and collaboration.

Responsibilities

• Develop and execute comprehensive verification plans for FPGA designs.
• Create and maintain test benches using UVM and SystemVerilog.
• Write and debug test cases to verify functionality and corner cases.
• Perform code coverage and functional coverage analysis.
• Identify and debug issues with design engineers.
• Document verification results and reports.
• Participate in design reviews and contribute to verification strategy.
• Stay up-to-date with verification methodologies and tools.

Skills

FPGA

SystemVerilog

UVM

QuestaSim

Synopsys VCS

Code Coverage

Debugging

Python

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

VHDL

Verilog

Job description

Mandatory Areas

Must Have Skills – FPGA Verification Engineer

Skill 1 – 8 + Years of in FPGA

Skill 2 – 5 +Years of Exp in UVM

Skill 2 – 5 +Years of Exp in System Verlilog

Location – Santa Clara, CA

Onsite Requirement - Y/N- Y

Number of days onsite – 5 Days

If Onsite – Office Address –

Job Description

We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.

Key Responsibilities

• Develop and execute comprehensive verification plans for FPGA designs.
• Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, SystemVerilog).
• Write and debug test cases to verify functionality, performance, and corner cases.
• Perform code coverage and functional coverage analysis.
• Identify and debug issues, working closely with design engineers to resolve them.
• Document verification results and provide clear and concise reports.
• Participate in design reviews and contribute to the overall verification strategy.
• Stay up-to-date with the latest verification methodologies and tools.
  
  

Skills Required

• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog and UVM verification methodology.
• Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
• Knowledge of code coverage and functional coverage analysis.
• Excellent debugging and problem-solving skills.
• Strong communication and collaboration skills.
  
  

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in FPGA verification.
• Experience with scripting languages (e.g., Python, Perl).
• Familiarity with hardware description languages (e.g., VHDL, Verilog).