FPGA Design Verification Engineer

Inabia-Software-; El Segundo (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Inabia-Software- in El Segundo, CA is seeking an FPGA Design Verification Engineer with 5+ years hands-on experience. You will develop SystemVerilog/UVM verification testbenches, create verification plans, and drive functional coverage across the FPGA design lifecycle.

Collaborate with hardware, firmware, and system engineering teams to build reusable verification components and support FPGA verification from planning to final sign-off. U.S. citizens only; Secret DoD clearance preferred.

Qualifications

• 5+ years of hands-on FPGA design verification experience.
• Strong knowledge of SystemVerilog and UVM.
• Experience with testbench development and verification planning.
• Functional coverage analysis and coverage closure.
• Experience building reusable verification components.
• C/C++ test development or hardware/software integration.
• Ability to work independently and troubleshoot issues.

Responsibilities

• Develop and maintain SystemVerilog and UVM-based verification testbenches.
• Create and execute verification plans, test scenarios, and functional tests.
• Develop reusable verification components and verification IP.
• Perform functional coverage analysis and drive coverage closure.
• Develop C-based tests and support hardware/software integration.
• Debug simulation failures and work with design teams to resolve verification issues.
• Support FPGA verification from initial planning through final verification sign-off.
• Collaborate with hardware, firmware, and system engineering teams.

Skills

SystemVerilog

UVM

Verification testbench development

Verification plans

Functional coverage

C/C++ test development

Hardware/software integration

Troubleshooting

Job description

We are currently hiring for an FPGA Design Verification Engineer for an opportunity based in El Segundo, California.

Job Title

FPGA Design Verification Engineer

Location

El Segundo, CA

Experience

5+ years

Work Authorization

U.S. Citizens only

Security Clearance

Secret DoD clearance preferred

Job Overview

We are looking for an experienced FPGA Design Verification Engineer with hands-on expertise in SystemVerilog, UVM, and verification testbench development. The ideal candidate will have experience developing verification plans, building reusable verification components, analyzing functional coverage, and supporting FPGA verification activities throughout the development lifecycle.

Key Responsibilities

• Develop and maintain SystemVerilog and UVM-based verification testbenches.
• Create and execute verification plans, test scenarios, and functional tests.
• Develop reusable verification components and verification IP.
• Perform functional coverage analysis and drive coverage closure.
• Develop C-based tests and support hardware/software integration.
• Debug simulation failures and work with design teams to resolve verification issues.
• Support FPGA verification from initial planning through final verification sign-off.
• Collaborate with hardware, firmware, and system engineering teams.

Required Skills

• At least 5 years of hands-on FPGA design verification experience.
• Strong knowledge of SystemVerilog and UVM.
• Experience with testbench development and verification planning.
• Functional coverage analysis and coverage closure.
• Experience developing reusable verification components.
• C/C++ test development or hardware/software integration experience.
• Ability to work independently and troubleshoot technical issues.

Preferred Experience

• SpaceWire protocol
• DDR4 memory interfaces
• SerDes connectivity
• Configuration, control, and telemetry systems
• Aerospace or defense-related systems
• Active Secret DoD security clearance

Please note

Please note that U.S. citizenship is mandatory for this position. A Secret DoD clearance is preferred.