FPGA Test & DFT Development Engineer

Altera; San Jose (CA); On-site; USD 106,000 - 154,000; Full time

Job summary

Altera in San Jose is seeking a Product Development Engineer to join the Manufacturing Content Development Engineering Group. You will architect, develop, validate, and productize high-quality manufacturing test content for FPGAs, ensuring top-yield and device quality.

You will lead DFT strategies (scan, BIST, test compression), collaborate with RTL teams, and drive test plans, patterns, and fault models to optimize test effort and cost.

Qualifications

• Bachelor's or Master's in Electrical Engineering with 3+ years in IC design/test.
• Experience with DFT methodologies and pattern development is required.
• Familiarity with Tessent tools and RTL/Synthesis/Verification flows.
• Strong scripting in Python, Perl, or TCL is preferred.

Responsibilities

• Develop and implement DFT strategies for FPGAs, including scan insertion and test compression.
• Collaborate with RTL design/verification to embed testability features.
• Define test plans, patterns, and fault models for coverage and yield.
• Maintain MBIST content flows and scripts for manufacturing tests.
• Perform pre-silicon test pattern simulations and validation before tape-out.
• Analyze results, debug silicon failures, and provide root cause analysis.
• Work with manufacturing to optimize test time, cost, and quality.
• Drive test time reduction via fallout data analysis across IPs.

Skills

IC design

DFT methods

Scan chains

Memory BIST

ATPG

IJTAG/JTAG

Scripting (Python/TCL)

Test time analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

TessentIJTAG

Tessent-MemoryBIST

FastScan

Tessent Shell

Job description

Altera in San Jose is seeking a Product Development Engineer to join the Manufacturing Content Development Engineering Group. You will architect, develop, validate, and productize high-quality manufacturing test content for FPGAs, ensuring top-yield and device quality.

You will lead DFT strategies (scan, BIST, test compression), collaborate with RTL teams, and drive test plans, patterns, and fault models to optimize test effort and cost.