FPGA Prototyping Debug & Runtime Infrastructure Engineer

Siemens EDA (Siemens Digital Industries Software); Wilsonville (OR); Hybrid; USD 90,000 - 162,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Siemens EDA in Wilsonville, Oregon is seeking an FPGA Hardware Design Engineer to join the prototyping R&D team. You will work on design, verification, and integration of RTL IP for our FPGA prototyping software and hardware platform.

You will implement IP blocks in Verilog/SystemVerilog, validate with simulations and real FPGA boards, and optimize timing and performance constraints using Xilinx Vivado and Intel PSG Quartus. Travel to sites may be required.

Qualifications

• BSEE or BSCE degree required.
• Proficiency in RTL design and FPGA/IP integration.
• Experience with Verilog/SystemVerilog and VHDL.

Responsibilities

• Design, implement, and maintain IP blocks in Verilog.
• Validate with simulation and FPGA boards.
• Develop and test related software components.
• RTL synthesis with timing constraints and flows.
• Provide customer support for deployed features.

Skills

RTL design

SystemVerilog/Verilog

VHDL

FPGA implementation

Vivado/Quartus

Python

C/C++

Linux

IP reuse

Debugging & timing

Education

BSEE or BSCE

Tools

Xilinx Vivado

Intel PSG Quartus

FPGA hardware boards

Job description

Siemens EDA in Wilsonville, Oregon is seeking an FPGA Hardware Design Engineer to join the prototyping R&D team. You will work on design, verification, and integration of RTL IP for our FPGA prototyping software and hardware platform.

You will implement IP blocks in Verilog/SystemVerilog, validate with simulations and real FPGA boards, and optimize timing and performance constraints using Xilinx Vivado and Intel PSG Quartus. Travel to sites may be required.