FPGA Platform Engineer: RTL to Silicon Prototyping (PCIe)

Normal Computing Corp.; New York (NY); On-site; USD 110,000 - 180,000; Full time

Job summary

Normal Computing Corp. is seeking an FPGA Design Engineer to own the bridge between RTL and physical silicon, bringing ASIC-inspired designs to life on FPGA platforms for pre-silicon validation and early software development.

You will lead FPGA prototyping platform bring-up, implement RTL for FPGA targets, and validate timing closure while collaborating with silicon, EDA, and research teams. Strong fluency in SystemVerilog/VHDL and PCIe, plus lab debugging, are essential.

Qualifications

• Proven industry experience taking FPGA designs from RTL to validated hardware.
• Strong SystemVerilog and/or VHDL for synthesis with Xilinx Vivado expertise.
• Hands-on experience implementing and debugging PCIe and AXI/AHB interfaces.
• Lab-based bring-up, timing closure, and high-speed link characterization.

Responsibilities

• Own the bridge between RTL and physical silicon for pre-silicon validation on FPGA.
• Implement RTL for FPGA targets and verify timing closure.
• Integrate in-house IP with vendor IP in the Xilinx ecosystem.
• Develop scripts and test infrastructure in Python/C++, and automate builds.
• Debug lab issues using oscilloscopes, logic analyzers, and ILA/Vivado Analyzer.

Skills

Python

C++

SystemVerilog

PCIe

Tools

Vivado

HAPS

VCU118

IP Integrator

Job description

Normal Computing Corp. is seeking an FPGA Design Engineer to own the bridge between RTL and physical silicon, bringing ASIC-inspired designs to life on FPGA platforms for pre-silicon validation and early software development.

You will lead FPGA prototyping platform bring-up, implement RTL for FPGA targets, and validate timing closure while collaborating with silicon, EDA, and research teams. Strong fluency in SystemVerilog/VHDL and PCIe, plus lab debugging, are essential.