Hardware Engineer (FPGA)

Normal Computing Corp.; New York (NY); On-site; USD 110,000 - 180,000; Full time

Job summary

Normal Computing Corp. is seeking an FPGA Design Engineer to own the bridge between RTL and physical silicon, bringing ASIC-inspired designs to life on FPGA platforms for pre-silicon validation and early software development.

You will lead FPGA prototyping platform bring-up, implement RTL for FPGA targets, and validate timing closure while collaborating with silicon, EDA, and research teams. Strong fluency in SystemVerilog/VHDL and PCIe, plus lab debugging, are essential.

Qualifications

• Proven industry experience taking FPGA designs from RTL to validated hardware.
• Strong SystemVerilog and/or VHDL for synthesis with Xilinx Vivado expertise.
• Hands-on experience implementing and debugging PCIe and AXI/AHB interfaces.
• Lab-based bring-up, timing closure, and high-speed link characterization.

Responsibilities

• Own the bridge between RTL and physical silicon for pre-silicon validation on FPGA.
• Implement RTL for FPGA targets and verify timing closure.
• Integrate in-house IP with vendor IP in the Xilinx ecosystem.
• Develop scripts and test infrastructure in Python/C++, and automate builds.
• Debug lab issues using oscilloscopes, logic analyzers, and ILA/Vivado Analyzer.

Skills

Python

C++

SystemVerilog

PCIe

Tools

Vivado

HAPS

VCU118

IP Integrator

Job description

• Validating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how
• As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization
• Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams
• FPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development
• RTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs
• IP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers)
• High-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers
• Post-Silicon Validation: Build FPGA-based “tester” designs for silicon bring-up, device characterization, and automated test environments
• Hardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows
• Lab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links

Strong Python for automation, test, and build toolingStartup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physicsHands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfacesProven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environmentExpert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog)Strong board-level bring-up and lab debugging skills on real hardwareCI/CD for hardware (GitLab CI, Docker-based build and test)SERDES tuning and signal integrity fundamentalsMixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog computeExperience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelinesVerification frameworks like Cocotb, UVM, or OSVVM