FPGA Platform Lead for Pre-Silicon AI Hardware

Normal Computing Corp.; New York (NY); On-site; USD 120,000 - 190,000; Full time

Job summary

Normal Computing is an applied AI company building hardware and software for semiconductor and AI infrastructure. We operate across New York City, Silicon Valley, London, Copenhagen, and Seoul, and seek an FPGA Design Engineer to bridge RTL and physical silicon, bringing ASIC designs to life on FPGA platforms for pre-silicon validation and early software development.

You will own FPGA platforms, implement RTL on FPGA targets, integrate IP, and develop the test infrastructure and software stack.

Qualifications

• Proven industry experience taking FPGA designs from RTL through timing closure.
• Expert-level SystemVerilog and/or VHDL; Xilinx Vivado proficiency.
• Hands-on experience with PCIe, AXI/AHB, SPI, UART, JTAG interfaces.
• Strong Python for automation and tooling.

Responsibilities

• Own FPGA platform selection, bring-up, and pre-silicon RTL validation.
• Adapt ASIC RTL to FPGA targets with multi-clock-domain designs.
• Integrate IP from vendors and internal designs; engage with AMD/Xilinx ecosystem.
• Design and validate high-speed PCIe I/O for accelerators in servers.
• Develop FPGA-based tester designs for silicon bring-up and characterization.
• Build the hardware-software stack with Python/C++ and regression flows.
• Lab debugging to root-cause timing and functional issues in real time.

Skills

SystemVerilog

VHDL

Xilinx Vivado

PCIe

Python

C++

Lab debugging

AXI/AHB

JTAG

Oscilloscopes

Tools

HAPS

VCU118

VPK180

Vivado IP Integrator

ILA/Vivado Analyzer

Job description

Normal Computing is an applied AI company building hardware and software for semiconductor and AI infrastructure. We operate across New York City, Silicon Valley, London, Copenhagen, and Seoul, and seek an FPGA Design Engineer to bridge RTL and physical silicon, bringing ASIC designs to life on FPGA platforms for pre-silicon validation and early software development.

You will own FPGA platforms, implement RTL on FPGA targets, integrate IP, and develop the test infrastructure and software stack.