FPGA Verification Engineer

Game 7 Staffing; California; Remote; USD 120,000 - 180,000; Full time

Job summary

Game 7 Staffing is seeking a verification engineer to architect UVM environments for AMD Xilinx FPGA/SoC designs used in flight-critical avionics. You will develop test plans, write SystemVerilog assertions, and build coverage with constrained-random sequences while collaborating on RTL reviews and hardware bring-up.

Ideal candidates have 2+ years in FPGA/ASIC verification, strong SystemVerilog/UVM/SVA in production, and familiarity with Questa/VCS/Xcelium/Vivado. Eligibility for a U.S.

Qualifications

• 2+ years FPGA/ASIC verification experience in production.
• Proficient in SystemVerilog, UVM methodology, and SVA in production.
• Experience with industry simulators (Questa, VCS, Xcelium, or Vivado) in production.
• Git-based workflows including code review in production.
• Linux development environments in production.
• Eligible for U.S. Secret security clearance.

Responsibilities

• Architect UVM verification environments for AMD FPGA/SoC designs.
• Develop verification plans with traceability to requirements.
• Author SystemVerilog Assertions for compliance checks.
• Build functional coverage models and drive code coverage analysis.
• Develop constrained-random test sequences for corner-case bugs.
• Establish regression suites, tracking coverage metrics.
• Debug failures using waveform tools and simulation logs.
• Collaborate on RTL reviews and bug resolution.
• Support hardware validation and board bring-up.
• Author verification closure reports and coverage summaries.

Skills

FPGA verification

ASIC verification

SystemVerilog

UVM

SVA

Questa

VCS

Xcelium

Vivado

Linux

Git

Tools

Questa

VCS

Xcelium

Vivado

Git

Job description

Location: Remote (U.S. only)

Headcount: 8

Contract: Full-time; Start: ASAP

Why Hiring: Need to enhance FPGA verification capabilities; Support rapid avionics development.

End Product: Verification environments for AMD (Xilinx) FPGA/SoC designs in flight-critical avionics.

Tech / Domain Environment

• SystemVerilog, UVM, SVA


• Linux


• DO-254, avionics standards


• Questa, VCS, Xcelium, Vivado

Job Duties

• Architect UVM verification environments for AMD FPGA/SoC designs.


• Develop verification plans with traceability to requirements.


• Author SystemVerilog Assertions for compliance checks.


• Build functional coverage models and drive code coverage analysis.


• Develop constrained-random test sequences for corner-case bugs.


• Establish regression suites, tracking coverage metrics.


• Debug failures using waveform tools and simulation logs.


• Collaborate on RTL reviews and bug resolution.


• Support hardware validation and board bring-up.


• Author verification closure reports and coverage summaries.

Must Haves

• 2+ years FPGA/ASIC verification experience in production.


• Proficient in SystemVerilog, UVM methodology, and SVA in production.


• Experience with industry simulators (Questa, VCS, Xcelium, or Vivado) in production.


• Git-based workflows including code review in production.


• Linux development environments in production.


• Eligible for U.S. Secret security clearance.

Nice to Haves

• 5+ years FPGA/ASIC verification experience.


• Master’s degree in Electrical or Computer Engineering.


• Experience with DO-254 and avionics verification standards.


• Familiarity with SVUnit or equivalent unit-testing frameworks.


• Experience with digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI.

Data / Perf Targets

Coverage metrics to closure, p99 < 95% for verification success.

Security / Clearance

• Eligible to obtain U.S. Secret security clearance.