FPGA/ASIC Hardware Engineer Intern — Fast-Paced Trading

Hudson River Trading; New York (NY); On-site; USD 235,000 - 293,000; Full time

Benefits offered by this job

Company-paid housing

Meals provided

Signing bonus

Job summary

Hudson River Trading (HRT) offers a Hardware Engineering Internship where you will design hardware in SystemVerilog and develop verification environments in Python. You’ll tackle projects in a fast-paced, real-time trading infrastructure while gaining insight into the financial markets and hardware development lifecycle.

You’ll start with training and then contribute to design and verification tasks, collaborating with teams across hardware and software interfaces to deliver impactful,

Qualifications

• You are a full-time student in a Computer Engineering, Electrical Engineering or related program
• You will be graduating and looking for full-time roles in 2028
• A thorough understanding of digital logic design and/or computer architecture
• Experience using a hardware design language such as SystemVerilog
• Familiarity with C++ and/or Python
• Knowledge of Linux and familiar with its command prompt
• A passion for technology and curiosity for how things work "under the hood"
• Exceptional problem solving skills
• Bonus: Familiarity with FPGAs or ASICs
• Bonus: Exposure to a hardware verification flow such as UVM, or open-source verification tools such as cocotb

Responsibilities

• Create hardware in SystemVerilog (design) and build complex modeling and testing environments in Python (verification)
• Work on independent projects within the internship program
• Learn about cutting edge FPGA/ASIC technology and hardware verification flows
• Jump into projects within the first two weeks of the program

Skills

Familiarity with C++/Python

Digital logic design/architecture

Problem solving

Curiosity about how things work

Linux command line

Tools

SystemVerilog

Python

C++

Job description

Hudson River Trading (HRT) offers a Hardware Engineering Internship where you will design hardware in SystemVerilog and develop verification environments in Python. You’ll tackle projects in a fast-paced, real-time trading infrastructure while gaining insight into the financial markets and hardware development lifecycle.

You’ll start with training and then contribute to design and verification tasks, collaborating with teams across hardware and software interfaces to deliver impactful,